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ORCID8th IEEE Symposium on Computer Arithmetic 1987: Como, Italy
- Mary Jane Irwin, Renato Stefanelli:
8th IEEE Symposium on Computer Arithmetic, ARITH 1987, Como, Italy, May 18-21, 1987. IEEE Computer Society 1987, ISBN 0-8186-0774-2
Signal and Image Processing
- Hiroshi Umeo:
A design of time-optimum and register-number-minimum systolic convolver. 5-12 - Steven G. Smith, Peter B. Denyer:
Synthesis of area-efficient VLSI architectures for vector and matrix multiplication. 13-20 - Rom-Shen Kao, Fred J. Taylor:
Implementation of the single modulus complex ALU. 21-27 - Isaac D. Scherson, Yiming Ma:
Vector computations on an orthogonal memory access multiprocessing system. 28-37
VLSI Adders and Multipliers
- Tony M. Carter:
Structured arithmetic tiling of integrated circuits. 41-48 - Tack-Don Han, David A. Carlson:
Fast area-efficient VLSI adders. 49-56 - Ramautar Sharma:
Area-time efficient arithmetic elements for VLSI systems. 57-62 - Luigi Ciminiera:
Parallel multipliers based on horizontal compressors. 63-69
High Speed Arithmetic Processors
- Jan Fandrianto:
Algorithm for high speed shared radix 4 division and radix 4 square-root. 73-79 - Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi
:
Design of high speed MOS multiplier and divider using redundant binary representation. 80-86 - Bidyut Kumar Bose, Li-fan Pei, George S. Taylor, David A. Patterson:
Fast multiply and divide for a VLSI floating-point unit. 87-94 - Victor Peng, Sridhar Samudrala, Moshe Gavrielov:
On the implementation of shifters, multipliers, and dividers in VLSI floating point units. 95-102
Elementary Function Evaluators
- Michel Cosnard, Alain Guyot, Bertrand Hochet, Jean-Michel Muller, Hassan Ouaouicha, P. Paul, Eytan Zysman:
The FELIN arithmetic coprocessor chip. 107-112 - Joseph R. Cavallaro, Franklin T. Luk:
CORDIC arithmetic for an SVD processor. 113-120 - Kai Hwang, H. C. Wang, Z. Xu:
Evaluating elementary functions with Chebyshev polynomials on pipeline nets. 121-128
Systolic Arithmetic Processors
- Thomas E. Hull, Marty S. Cohen:
Toward an ideal computer arithmetic. 131-138 - Frank W. J. Olver:
A closed computer arithmetic. 139-143 - Frank W. J. Olver, Peter R. Turner:
Implementation of level-index arithmetic using partial table look-up. 144-147 - James Demmel:
On error analysis in arithmetic with varying relative precision. 148-152 - Hozumi Hamada:
A new real number representation and its operation. 153-157 - Bertrand Hochet, Patrice Quinton, Yves Robert:
Systolic solution of linear systems over GF(p) with partial pivoting. 161-168 - Poras T. Balsara, Robert Michael Owens:
Systolic & semi-systolic digit serial multipliers. 169-173 - Behrooz Parhami:
Systolic up/down counters with zero and sign detection. 174-178
On-Line Arithmetic Processors
- Paul K.-G. Tu, Milos D. Ercegovac:
A radix-4 on-line division algorithm. 181-187 - Hai-Xiang Lin, Henk J. Sips:
A novel floating-point online division algorithm. 188-195 - Milos D. Ercegovac, Tomás Lang:
On-line scheme for computing rotation factors. 196-203 - Peter Kornerup, David W. Matula:
A bit-serial arithmetic unit for rational arithmetic. 204-211 - Attilio Colagrossi, Alfonso Miola:
A normalization algorithm for truncated p-adic arithmetic. 212-216
Fault-Tolerant Arithmetic Codes and Processors
- G. Robert Redinbo:
Protecting convolution-type aritmetic array calculations with generalized cyclic codes. 219-225 - James E. Robertson:
Error detection and correction for addition and subtraction, through use of higher radix extensions of hamming codes. 226-229 - Vincenzo Piuri:
Fault-tolerant systolic arrays: An approach based upon residue arithmetic. 230-238
Numerical Error Control
- Geoff Barrett:
A formal approach to rounding. 247-254 - J. Du Croz, M. Pont:
The development of a floating-point validation package. 255 - Reinhard Kirchner, Ulrich W. Kulisch:
Arithmetic for vector processors. 256-269 - Günter Schumacher:
Computer arithmetic and ill-conditioned algebraic problems. 270-276
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