35. DAC 1998: San Francico, California, USA

Executive Plenary Panel

Interfaces for Design Reuse

Analog and Mixed-Signal Design Tools

University Design Contest

Embedded System Design and Exploration

Taming Noise in Deep-Submicron Digital Designs

Control and Data Driven High Level Synthesis

Synthesis Flow in Deep Submicro Technologies

Environment for Collaborative Design

New Methods in Functional Verification


System-Level Power Optimization

Boolean Methods

Extraction and Modeling for Interconnect

Processor Design and Simulation


Performance Modeling and Characterization for Embedded Systems

Advances in Placement and Partitioning

Parasitic Device Extraction and Interconnect Modeling

Design Optimization for DSP


Bridging the Gap Between Simulation and Formal Verification

Logic Optimization

Routing for Performance and Crosstalk

Practical Optimization Methodologies for High Performance Design

RF IC design Methodology

Theory and Practice in High Level Synthesis

BDD Approximation Techniques

Interconnect Modeling and Timing Simulation

Low Power Design Using Multiple Thresholds and Supplies


Software Synthesis and Retargetable Compilation

Formal Methods in Functional Verification

Core Test and BIST

Interconnect Analysis and Reliability in Deep Sub-Micron


Timing Analysis

New Techniques in State Space Explorations

Advanced ATPG Techniques

Practical Experience of Funtional Verification for Complex ICs


Fast Functiona Simulation

Power Estimation and Modeling

Technology Mapping for Programmable Logic