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ORCIDDASIP 2018: Porto, Portugal
- 2018 Conference on Design and Architectures for Signal and Image Processing, DASIP 2018, Porto, Portugal, October 10-12, 2018. IEEE 2018, ISBN 978-1-5386-8237-1
Session: Architectures for efficient numerical computation
- Florian Kästner, Florian Werner, Erman Seydioglu, Michael Hübner:
Design and Open Source Implementation of a Reconfigurable Hardware Model Predicitive Controller Using Online Optimization. 1-6 - Gibin ChackoGeorge
, Abhishek Moitra, Sriyash Caculo, A. Amalin Prince:
Efficient Architecture for Implementation of Hermite Interpolation on FPGA. 7-12 - Adrian E. Sapio, Shuvra S. Bhattacharyya, Marilyn Wolf:
Efficient Solving of Markov Decision Processes on GPUs Using Parallelized Sparse Matrices. 13-18 - Ahmed M. Abdelsalam, Ahmed Elsheikh, Jean-Pierre David, J. M. Pierre Langlois:
POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA. 19-24
Session: Implementation of video processing algorithms - I
- Andrea Petreto, Arthur M. Hennequin, Thomas Koehler, Thomas Romera, Yohan Fargeix, Boris Gaillard, Manuel Bouyer, Quentin L. Meunier, Lionel Lacassagne:
Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU Architectures. 25-30 - Orlando Chuquimia, Andréa Pinna, Christophe Marsala, Xavier Dray, Bertrand Granado:
FPGA-Based Real Time Embedded Hough Transform Architecture for Circles Detection. 31-36 - Marcin Kowalczyk, Dominika Przewlocka, Tomasz Kryjak:
Real-Time Implementation of Contextual Image Processing Operations for 4K Video Stream in Zynq UltraScale+ MPSoC. 37-42
Session: Implementation of video processing algorithms - II
- Ahmet Can Mert, Ercan Kalali, Ilker Hamzaoglu:
A Low Power Versatile Video Coding (VVC) Fractional Interpolation Hardware. 43-47 - Marc Reichenbach, Lukas Liebischer, Steffen Vaas, Dietmar Fey:
Comparison of Lane Detection Algorithms for ADAS Using Embedded Hardware Architectures. 48-53 - Kazuya Uetsuhara, Akane Tahara, Taito Manabe, Yuichiro Shibata:
Implementation of a Real-Time Image-Based Vibration Detection and Adaptive Filtering on an FPGA. 54-59
Session: Demo Session
- Karol Radwan, Tomasz Kryjak, Marek Gorgon:
Hardware-Software Implementation of a SFM Module for Navigation an Unmanned Aerial Vehicles-A Demo. 60-61 - Safouane Noubir, Yannick Bornat:
Real-Time Analysis of Living Biological Cell Activity. 62-63
Session: European research projects
- Ariel Podlubne, Julian Haase, Lester Kalms, Gökhan Akgün, Muhammad Ali, Habib Ulhasan Khar, Ahmed Kamal, Diana Göhringer:
Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration. 64-69 - Harry Sidiropoulos, George Chatzikonstantis, Dimitrios Soudris, Christos Strydis:
The VINEYARD Framework for Heterogeneous Cloud Applications: The BrainFrame Case. 70-75
Session: GPU acceleration of algorithms
- Arthur M. Hennequin, Lionel Lacassagne, Laurent Cabaret, Quentin L. Meunier:
A new Direct Connected Component Labeling and Analysis Algorithms for GPUs. 76-81 - Rokiatou Diarra, Alain Mérigot, Bastien Vincke:
Exploring Performance Improvement Opportunities in Directive-Based GPU Programming. 82-87 - Scott Marshall, Garrett M. Vanhoy, Ali Akoglu, Tamal Bose, Bo Ryu:
GPU Based Quarter Spectral Correlation Density Function. 88-93
Session: Going beyond Moore's law
- Sivakumar Chidambaram, Alexandre Riviello, J. M. Pierre Langlois, Jean-Pierre David:
Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors. 94-99 - Petr Dobiás, Emmanuel Casseau, Oliver Sinnen:
Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems. 100-105 - Jani Boutellier, Henri Lunnikivi:
Design Flow for Portable Dataflow Programming of Heterogeneous Platforms. 106-111 - Georgios Georgakarakos, Johan Lilius:
Efficient Task-Based Code Generation for SDF Graph Execution on Multicore Processors. 112-117
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