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Semantic Scholar3. EDCC 1999: Prague, Czech Republic
Jan Hlavicka, Erik Maehle, András Pataricza:
Dependable Computing - EDCC-3, Third European Dependable Computing Conference, Prague, Czech Republic, September 15-17, 1999, Proceedings. Lecture Notes in Computer Science 1667, Springer 1999, ISBN 3-540-66483-1
Dependability Modelling
- Andrea Bondavalli, Ivan Mura, Kishor S. Trivedi:
Dependability Modelling and Sensitivity Analysis of Scheduled Maintenance Systems. 7-23 - Mourad Rabah, Karama Kanoun:
Dependability Evaluation of a Distributed Shared Memory Multiprocessor System. 42-62
Panel
Fast Abstracts
Protocols
- Assia Doudou, Benoît Garbinato, Rachid Guerraoui, André Schiper:
Muteness Failure Detectors: Specification and Implementation. 71-87 - Henrik Lönn:
A Fault Tolerant Clock Synchronization Algorithm for Systems with Low-Precision Oscillators. 88-105 - Luís Moura Silva, João Gabriel Silva:
An Experimental Evaluation of Coordinated Checkpointing in a Parallel Machine. 124-142
Fault Injection 1
- Manuel Rodríguez, Frédéric Salles, Jean-Charles Fabre, Jean Arlat:
MAFALDA: Microkernel Assessment by Fault Injection and Design Aid. 143-160 - Peter Folkesson, Johan Karlsson:
Considering Workload Input Variations in Error Coverage Estimation. 171-190
Fault Injection 2
- Daniel Gil, R. Martínez, J. V. Busquets, Juan Carlos Baraza, Pedro J. Gil:
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System. 191-208 - João Carlos Cunha, Mário Zenha Rela, João Gabriel Silva:
Can Software Implemented Fault-Injection Be Used on Real-Time Systems?. 209-228
Safety
- Toshihito Shirai, Masayoshi Sakai, Koichi Futsuhara, Masao Mukaidono:
A Method for Implementing a Safety Control System Based on Its Separation into Safety-Related and Non-Safety-Related Parts. 239-250
Hardware Testing
- Jerzy W. Greblicki, Stanislaw J. Piestrak:
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits. 251-266 - Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos:
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. 267-282 - Stefano Chessa, B. Sallay, Piero Maestrini:
Diagnostic Model and Diagnosis Algorithm of a SIMD Computer. 283-302
Built-In Self-Test
- Ondrej Novák:
Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata. 303-320 - Tomasz Garbolino, Andrzej Hlawiczka:
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits. 321-338 - Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich:
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. 339-350
Networks and Distributed Systems
- Michael Mock, Edgar Nett, Stefan Schemmer:
Efficient Reliable Real-Time Group Communication for Wireless Local Area Networks. 380-400
Software Testing and Self-Checking
- Hélène Waeselynck, Pascale Thévenod-Fosse:
A Case Study in Statistical Testing of Reusable Concurrent Objects. 401-418 - Yung-Yuan Chen:
Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring. 437-454
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last updated on 2017-06-23 18:49 CEST by the dblp team