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ORCIDFPT 2015: Queenstown, New Zealand
- 2015 International Conference on Field Programmable Technology, FPT 2015, Queenstown, New Zealand, December 7-9, 2015. IEEE 2015, ISBN 978-1-4673-9091-0
Oral Session 01: Applications I
- Junyi Xie, Xinyu Niu, Andy K. S. Lau, Kevin K. Tsia, Hayden Kwok-Hay So
:
Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy. 1-8 - James Arram, Moritz Pflanzer, Thomas Kaplan, Wayne Luk:
FPGA acceleration of reference-based compression for genomic data. 9-16 - Kubilay Atasu:
Leftmost longest regular expression matching in reconfigurable logic. 17-23 - Andrew Bitar, Mohamed S. Abdelfattah, Vaughn Betz:
Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA. 24-31
Oral Session 02: High Level Synthesis: Debugging
- Fatemeh Eslami, Steven J. E. Wilton:
An adaptive virtual overlay for fast trigger insertion for FPGA debug. 32-39 - Jeffrey Goeders, Steven J. E. Wilton:
Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs. 40-47 - Joshua S. Monson, Brad L. Hutchings:
Using source-to-source compilation to instrument circuits for debug with High Level Synthesis. 48-55
Oral Session 03: Architecture
- Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So:
QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay. 56-63 - Hyunseok Park, Shreel Vijayvargiya, André DeHon:
Energy minimization in the time-space continuum. 64-71 - Alex Rodionov, Jonathan Rose:
Automatic FPGA system and interconnect construction with multicast and customizable topology. 72-79 - Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne:
Improved carry chain mapping for the VTR flow. 80-87
Oral Session 04
- Kevin E. Murray, Vaughn Betz:
HETRIS: Adaptive floorplanning for heterogeneous FPGAs. 88-95 - Elias Vansteenkiste, Alireza Kaviani, Henri Fraisse:
Analyzing the divide between FPGA academic and commercial results. 96-103 - Jasmina Vasiljevic, Ralph Wittig, Paul Schumacher, Jeff Fifield, Fernando Martinez-Vallina, Henry Styles, Paul Chow:
OpenCL library of stream memory components targeting FPGAs. 104-111 - Vincent Mirian, Paul Chow:
Exploring pipe implementations using an OpenCL framework for FPGAs. 112-119
Oral Session 05: Applications II
- Shuanglong Liu, Grigorios Mingas, Christos-Savvas Bouganis:
An exact MCMC accelerator under custom precision regimes. 120-127 - Jianfeng Zhang, Paul Chow, Hengzhu Liu:
FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC. 128-135 - Stephen Tridgell, Duncan J. M. Moss, Nicholas J. Fraser, Philip Heng Wai Leong:
Braiding: A scheme for resolving hazards in kernel adaptive filters. 136-143
Oral Session 06: High Level Synthesis II
- Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson, George A. Constantinides:
Custom-sized caches in application-specific memory hierarchies. 144-151 - Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson:
Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. 152-159 - Ian Graves, Adam M. Procter, William L. Harrison, Gerard Allwein:
Provably Correct Development of reconfigurable hardware designs via equational reasoning. 160-171
Poster Session P1
- Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow:
Behavioral-level IP integration in high-level synthesis. 172-175 - Jens Huthmann, Andreas Koch:
Optimized high-level synthesis of SMT multi-threaded hardware accelerators. 176-183 - Bajaj Ronak, Suhaib A. Fahmy:
Minimizing DSP block usage through multi-pumping. 184-187 - Jifang Jin, Jian Yan, Xuegong Zhou, Lingli Wang:
An adaptive cross-layer fault recovery solution for reconfigurable SoCs. 188-191 - Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich:
A co-design approach for accelerated SQL query processing via FPGA-based data filtering. 192-195 - Yubin Li, Yuliang Sun, Guohao Dai, Yuzhi Wang, Jiacai Ni, Yu Wang, Guoliang Li, Huazhong Yang:
A self-aware data compression system on FPGA in Hadoop. 196-199
Poster Session P2
- Mengyuan Gu, Kaiyuan Guo, Wenqiang Wang, Yu Wang, Huazhong Yang:
An FPGA-based real-time simultaneous localization and mapping system. 200-203 - Size Xiao, Adam Postula, Neil W. Bergmann:
Hardware design of a fast, parallel Random Tree path planner. 204-207 - James Stanley Targett, Xinyu Niu, Francis P. Russell, Wayne Luk, Stephen Jeffress, Peter D. Düben:
Lower precision for higher accuracy: Precision and resolution exploration for shallow water equations. 208-211 - Sebastian Meisner, Marco Platzner:
Comparison of thread signatures for error detection in hybrid multi-cores. 212-215 - Donald G. Bailey, Sharmil Randhawa, Jim S. Jimmy Li:
Advanced Bayer demosaicing on FPGAs. 216-220 - Liwei Yang, Magzhan Ikram, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:
JIT trace-based verification for high-level synthesis. 228-231
PhD Forum
- Jason Motha, Andrew Bainbridge-Smith, Steve Weddell:
Cryptographic techniques in redundant number systems. 232-235 - Faisal Mahmood, Mart Toots, Lars-Goran Ofverstedt, Ulf Skoglund:
2D Discrete Fourier Transform with simultaneous edge artifact removal for real-time applications. 236-239 - Haomiao Wang, Oliver Sinnen:
FPGA based acceleration of FDAS module for Pulsar Search. 240-243 - Yuki Murakami:
FPGA implementation of a SIMD-based array processor with torus interconnect. 244-247
Demonstration Session
- Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok:
An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine. 248-251 - Donald G. Bailey:
Smart camera for Trax playing robot. 252-255
Design Competition
- Ryo Okuda, Tomohiro Tanaka, Keisuke Yamamoto, Takumu Yahagi, Kazuya Tanigawa:
Development of a Trax Artificial Intelligence algorithm using path and edge. 256-259 - Takumi Fujimori, Tomoya Akabe, Yoshizumi Ito, Kouta Akagi, Shinya Furukawa, Hiroki Shinba, Aoi Tanibata, Minoru Watanabe:
FPGA Trax Solver based on a neural network design. 260-263 - Qing Lu, Chiu-Wing Sham, Francis C. M. Lau:
An architecture-algorithm co-design of artificial intelligence for Trax player. 264-267 - Akira Kojima:
An Implementation of Trax player using programmable SoC. 268-271 - Naru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano:
Trax solver on Zynq with Deep Q-Network. 272-275
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