Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID13th IOLTS 2007: Heraklion, Crete, Greece
- 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece. IEEE Computer Society 2007, ISBN 0-7695-2918-6
Test Technology Educational Program (TTEP) 2007 Full-Day Tutorial
- Subhasish Mitra, Pia N. Sanda, Norbert Seifert:
Soft Errors: Technology Trends, System Effects, and Protection Techniques. 4
Keynote Talk
- Mark Derbey:
Soft-Errors Phenomenon Impacts on Design for Reliability Technologies. 7
Invited Talk
- Sanjiv Taneja:
Accelerating Yield Ramp through Real-Time Testing. 11
Session 1: Reliability Issues in Nanometer Technologies
- Jaume Abella
, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González:
Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. 15-22 - Ming Zhang, T. M. Mak, James W. Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu:
Design for Resilience to Soft Errors and Variations. 23-28 - Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia:
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. 29-36
Session 2: Network-on-Chip Reliability and Fault Tolerance
- Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve A. Saleh:
Essential Fault-Tolerance Metrics for NoC Infrastructures. 37-42 - Daniele Rossi, Paolo Angelini, Cecilia Metra:
Configurable Error Control Scheme for NoC Signal Integrity. 43-48 - Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi:
An Analytical Model for Reliability Evaluation of NoC Architectures. 49-56
Session 3: Secure Systems
- Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. 57-62 - Nadine Buard, Florent Miller, Cédric Ruby, Rémi Gaillard:
Latchup effect in CMOS IC: a solution for crypto-processors protection against fault injection attacks? 63-70 - Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi:
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding. 71-78
Session 4: Large Scale Dependability
- Nikolaos G. Bartzoudis, Klaus D. McDonald-Maier:
Online monitoring of FPGA-based co-processing engines embedded in dependable workstations. 79-84 - Michel Pignol:
Methodology and Tools Developed for Validation of COTS-based Fault-Tolerant Spacecraft Supercomputers. 85-92 - Fabian Vargas, Leonardo Piccoli, Juliano Benfica, Antonio A. de Alecrim Jr., Marlon Moraes:
Time-Sensitive Control-Flow Checking for Multitask Operating System-Based SoCs. 93-100
Session 5: Dependability of Processors, SoCs and Asynchronous Circuits
- Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena:
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. 101-106 - Paolo Bernardi, Letícia Maria Veiras Bolzani, Matteo Sonza Reorda:
A Hybrid Approach to Fault Detection and Correction in SoCs. 107-112 - Yannick Monnet, Marc Renaudin, Régis Leveugle:
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. 113-120
Special Session 1: Aging and Wearout Issues and Mitigation Approaches
- Antonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor:
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design. 121 - T. M. Mak:
Infant Mortality--The Lesser Known Reliability Issue. 122 - Subhasish Mitra:
Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout. 123
Keynote Talk
- Krisztián Flautner:
Blurring the Layers of Abstractions: Time to Take a Step Back? 127
Session 6: Radiation Effects
- Tino Heijmen:
Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMs. 131-136 - Claudia Rusu, Antonin Bougerol, Lorena Anghel, Cécile Weulersse, Nadine Buard, S. Benhammadi, Nicolas Renaud, Guillaume Hubert, Frederic Wrobel, Thierry Carrière, Rémi Gaillard:
Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells. 137-145 - Marta Bagatin, Giorgio Cellere, Simone Gerardin, Alessandro Paccagnella, Angelo Visconti, Silvia Beltrami, M. Maccarrone:
Single Event Effects in 1Gbit 90nm NAND Flash Memories under Operating Conditions. 146-151 - Alodeep Sanyal, Sandip Kundu:
On Derating Soft Error Probability Based on Strength Filtering. 152-160
Session 7: Signal Integrity and Error Compensation
- Partha Pratim Pande, Amlan Ganguly, Brett Feero, Cristian Grecu:
Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics. 161-166 - Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. 167-172 - Muhammad Mudassar Nisar, Maryam Ashouei, Abhijit Chatterjee:
Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums. 173-182
Special Session 2: Panel: SER Trends in 45nm and Beyond
Session 8: Posters
- X. Cano, Sebastià A. Bota, Ricardo Graciani Diaz, David Gascon, A. Herms, Albert Comerma, Jaume Segura, Lluís Garrido:
Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. 183-184 - Olivier Faurax, Assia Tria, Laurent Freund, Frédéric Bancel:
Robustness of circuits under delay-induced faults : test of AES with the PAFI tool. 185-186 - Riccardo Mariani, Gabriele Boschi:
A systematic approach for Failure Modes and Effects Analysis of System-On-Chips. 187-188 - Costas Argyrides, Dhiraj K. Pradhan:
Highly Reliable Power Aware Memory Design. 189-190 - Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
Accelerating Soft Error Rate Testing Through Pattern Selection. 191-193 - Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante:
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. 194-196 - Ioannis Voyiatzis:
Embedding test patterns into Low-Power BIST sequences. 197-198 - Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache:
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes. 199-200 - Ilia Polian, Damian Nowroth, Bernd Becker:
Identification of Critical Errors in Imaging Applications. 201-202 - Franz X. Ruckerbauer, Georg Georgakos:
Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena. 203-204 - Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale:
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. 205-206 - Jimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan:
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. 207-208
Session 9: Fault Tolerance
- Karthik Pattabiraman, Zbigniew Kalbarczyk, Ravishankar K. Iyer:
Automated Derivation of Application-aware Error Detectors using Static Analysis. 211-216 - Manuel G. Gericota, Luís F. Lemos, Gustavo R. Alves, José M. Ferreira:
On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs. 217-222 - K. T. Gardiner, Alexandre Yakovlev, Alexandre V. Bystrov:
A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits. 223-230
Session 10: On-Line Testing for Analog, Mixed-Signal, RF and Delay Defect Tolerance
- John C. Liobe, Martin Margala:
Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test. 231-236 - Emmanuel Simeu, Salvador Mir, R. Kherreddine, Hoang Nam Nguyen:
Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches. 237-243 - Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy:
Tolerance to Small Delay Defects by Adaptive Clock Stretching. 244-252
Special Session 3: Fault-Tolerant and Self-Adapting Design to Mitigate Power, Yield and Reliability Issues in Upcoming Process Nodes
- Asen Asenov:
Statistical Device Variability and its Impact on Yield and Performance. 253 - Davide Pandini:
Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies. 254 - Michael Nicolaidis:
GRAAL: A Fault-Tolerant Architecture for Enabling Nanometric Technologies. 255
Special Session 4: Reconfiguration and Fault Tolerance in Future Massively Parallel Multi-Core Chips
- Jacques Henri Collet, Piotr Zajac:
Resilience, Production Yield and Self-Configuration in the Future Massively Defective Nanochips. 259 - Xavier Vera, Jaume Abella:
Surviving to Errors in Multi-Core Environments. 260 - Krisztián Flautner:
Architectural Trade-Offs for Fault Tolerant Multi-Core Systems. 261
Session 11: Processor-Based Testing
- Letícia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero:
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores. 265-270 - Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis:
A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs. 271-276 - R. Frost, D. Rudolph, Christian Galke, René Kothe, Heinrich Theodor Vierhaus:
A Configurable Modular Test Processor and Scan Controller Architecture. 277-284 - Steffen Tarnick:
Design of Embedded m-out-of-n Code Checkers Using Complete Parallel Counters. 285-292 - Snehal Udar, Dimitri Kagaris:
LFSR Reseeding with Irreducible Polynomials. 293-298
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-17 20:30 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
