Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDLCTES 2010: Stockholm, Sweden
- Jaejin Lee, Bruce R. Childers:
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, LCTES 2010, Stockholm, Sweden, April 13-15, 2010. ACM 2010, ISBN 978-1-60558-953-4
Memory systems
- Minming Li
, Chun Jason Xue, Tiantian Liu, Yingchao Zhao:
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture. 1-8 - Robert Pyka, Felipe Klein, Peter Marwedel, Stylianos Mamagkakis:
Versatile system-level memory-aware platform description approach for embedded MPSoCs. 9-16 - Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunheung Paek:
Operation and data mapping for CGRAs with multi-bank memory. 17-26
Streaming and synchronous languages
- Mohammad H. Foroozannejad, Matin Hashemi, Trevor L. Hodges, Soheil Ghiasi:
Look into details: the benefits of fine-grain streaming buffer analysis. 27-36 - Simon Perathoner, Tobias Rein, Lothar Thiele, Kai Lampka, Jonas Rox:
Modeling structured event streams in system level performance analysis. 37-46 - Jens Brandt, Klaus Schneider, Sandeep K. Shukla:
Translating concurrent action oriented specifications to synchronous guarded actions. 47-56
Synthesis, timing analysis and design exploration
- Gwenaël Delaval, Hervé Marchand, Éric Rutten:
Contracts for modular discrete controller synthesis. 57-66 - Marc Schlickling, Markus Pister:
Semi-automatic derivation of timing models for WCET analysis. 67-76 - Ines Viskic, Lochi Yu, Daniel Gajski:
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications. 77-84
Compiler techniques
- Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan:
Compiler directed network-on-chip reliability enhancement for chip multiprocessors. 85-94 - Prasad A. Kulkarni, Michael R. Jantz, David B. Whalley:
Improving both the performance benefits and speed of optimization phase sequence searches. 95-104 - Weijia Li, Youtao Zhang:
An efficient code update scheme for DSP applications in mobile embedded systems. 105-114
Design frameworks and tools
- John Robert Wernsing, Greg Stitt:
Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing. 115-124 - Matthias Biehl, De-Jiu Chen, Martin Törngren:
Integrating safety analysis into the model-based development toolchain of automotive embedded systems. 125-132 - Sebastian Fischmeister, Yanmeng Ba:
Sampling-based program execution monitoring. 133-142
Caching and buffer management
- Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul:
Cache vulnerability equations for protecting data in embedded processor caches from soft errors. 143-152 - Sebastian Altmeyer, Claire Maiza, Jan Reineke:
Resilience analysis: tightening the CRPD bound for set-associative caches. 153-162 - Yi Wang, Duo Liu, Meng Wang, Zhiwei Qin, Zili Shao, Yong Guan:
RNFTL: a reuse-aware NAND flash translation layer for flash memory. 163-172
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-19 19:19 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
