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ORCIDMTDT 2003: San José, CA, USA
- 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA. IEEE Computer Society 2003, ISBN 0-7695-2004-9
DRAM for Leading Edge Applications
- Betty Prince:
Application Specific DRAMs Today. 7-13 - Bruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott
:
A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing. 14-19 - Youhei Zenda, Koji Nakamae, Hiromu Fujioka:
Cost Optimum Embedded DRAM Design by Yield Analysis. 20-
Fault Analysis and Test Generation and Verification
- Zaid Al-Ars, Ad J. van de Goor:
Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. 27-32 - Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor:
A Fault Primitive Based Analysis of Linked Faults in RAMs. 33-
Enhanced Testing Techniques
- Jörg E. Vollrath:
Output Timing Measurement Using an Idd Method. 43-46 - Baosheng Wang, Josh Yang, André Ivanov:
Reducing Test Time of Embedded SRAMs. 47-52 - Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li:
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. 53-
Memory Roadmap, Yield and Optimization
- Roger Barth:
ITRS Commodity Memory Roadmap. 61-63 - Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri:
Optimal Spare Utilization in Repairable and Reliable Memory Cores. 64-71 - Robert C. Aitken:
Applying Defect-Based Test to Embedded Memories in a COT Model. 72-
Memory Design Techniques
- Jean Michel Daga, Caroline Papaix, Emmanuel Racape, Marylene Combe, Vincent Sialelli, Jeanine Guichaoua:
A 40ns Random Access Time Low Voltage 2Mbits EEPROM Memory for Embedded Applications. 81-85 - Daniel Salamon, Bruce F. Cockburn:
An Electrical Simulation Model for the Chalcogenide Phase-Change Memory Cell. 86-
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