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ORCIDSBCCI 2008: Gramado, Brazil
- Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta:
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008. ACM 2008, ISBN 978-1-60558-231-3
Tutorials
- Paul G. A. Jespers:
Sizing CMOS circuits by means of the gm/ID methodology and a compact model. 1 - David Z. Pan:
Synergistic modeling and optimization for nanometer IC design/manufacturing integration. 2 - Gordon W. Roberts:
Test Methods For Sigma-Delta Data Converters and Related Devices. 3 - Naveen K. Yanduru:
Highly integrated, re-configurable RF front-ends in deep sub-micron CMOS: (with an example of a WCDMA, GSM/GPRS/EDGE receiver without inter-stage SAW filter). 4
Keynote
- Giovanni De Micheli:
System-level design technologies for heterogeneous distributed systems. 5
Invited talks
- David Z. Pan:
Lithography friendly routing: from construct-by-correction to correct-by-construction. 6 - Gordon W. Roberts, Mohammed Ali-Bakhshian:
Time-domain analog signal processing techniques. 7 - Ahmed Maine Jerraya:
System design for 3D Silicon integration. 8
Technical panel
- Ricardo P. Jacobi, Reinaldo A. Bergamaschi:
Challenges of the nanoscale era. 9
Design for yield
- Yanming Jia, Yici Cai, Xianlong Hong:
Full-chip routing system for reducing Cu CMP & ECP variation. 10-15 - Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean-Michel Portal:
Metal filling impact on standard cells: definition of the metal fill corner concept. 16-21 - André V. Fidalgo
, Gustavo R. Alves, Manuel G. Gericota, José Manuel Martins Ferreira:
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures. 22-27 - André Borin Soares, Alexsandro Cristovão Bonatto, Altamiro Amadeu Susin:
A new march sequence to fit DDR SDRAM test in burst mode. 28-33 - Eduardo Luis Rhod, Luigi Carro:
An efficient test and characterization approach for nanowire-based architectures. 34-39
Architectural design and synthesis in embedded systems
- Abner Corrêa Barros, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Paulo Sérgio Brandão do Nascimento, Ângelo Mazer, João Paulo Fernandes Barbosa, Bruno P. Neves, Ismael Santos, Manoel Eusébio de Lima:
Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA. 40-45 - Giancarlo Covolo Heck, Roberto A. Hexsel:
The performance of pollution control victim cache for embedded systems. 46-51 - Wagner Vieira Silvério, Janaína Domingues Costa, João Leonardo Fragoso, Julio Leão Silva Jr.:
Low-area ASIC implementation for configurable coefficients FIR pulse shape filters of digital TV systems. 52-57 - Levent Aksoy, Ece Olcay Günes:
An approximate algorithm for the multiple constant multiplications problem. 58-63 - Levent Aksoy, Ece Olcay Günes:
Area optimization algorithms in high-speed digital FIR filter synthesis. 64-69
High performance circuits
- Rafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías, Diego Vázquez, Adoración Rueda, José Luis Huertas:
A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model. 70-75 - Fernando da Rocha Paixão Cortes, Sergio Bampi:
A 40mhz 70db gain variable gain amplifier design using the gm/id design method. 76-80 - Juan Mateus, Elkim Roa, Hugo Daniel Hernández, Wilhelmus A. M. Van Noije:
A 2.7ua sub1-v voltage reference. 81-84 - Luciano Severino de Paula, Altamiro Amadeu Susin, Sergio Bampi:
A wide band CMOS differential voltage-controlled ring oscillator. 85-89 - Marcio Barbosa Lucks, Nobuo Oki:
RBF circuits based on folded cascode differential pairs. 90-93
Design for reliability
- Jader A. De Lima, Wallace A. Pimenta:
A current limiter for DC/DC regulators with internal compensation for process and temperature. 94-99 - Pietro Maris Ferreira, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia:
Current mode read-out circuit for infrared photodiode applications in 0.35 mum cmos. 100-104 - Eduardo Conrad Jr., Fernando da Rocha Paixão Cortes, Sergio Bampi, Alessandro Girardi:
Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors. 105-110 - Claas Cornelius, Frank Sill, Hagen Sämrow, Jakob Salzmann, Dirk Timmermann, Diógenes Cecilio da Silva Jr.:
Encountering gate oxide breakdown with shadow transistors to increase reliability. 111-116
Advances in low power design and power management
- Gustavo Wilke, Renan Fonseca, Cecilia Mezzomo, Ricardo Reis:
A novel scheme to reduce short-circuit power in mesh-based clock architectures. 117-122 - Mahmoud Ben Naser, Csaba Andras Moritz:
Power and performance tradeoffs with process variation resilient adaptive cache architectures. 123-128 - Eduardo Ribeiro da Silva, Ivan Carlos Ribeiro do Nascimento, Frank Herman Behrens, Marcos Mauricio Pelicia, Remerson Stein Kickhofel, Ricardo Maltione:
Power management techniques for very low consumption and EMI reduction in automotive applications. 129-133 - Gustavo Rau de Almeida Callou, Paulo Romero Martins Maciel, Ermeson Carneiro de Andrade, Bruno Costa e Silva Nogueira, Eduardo Antonio Guimarães Tavares:
A coloured petri net based approach for estimating execution time and energy consumption in embedded systems. 134-139 - Felipe Ghellar, Marcelo Lubaszewski:
A novel AES cryptographic core highly resistant to differential power analysis attacks. 140-145
Circuit optmization methods and tools
- Jorge Oliveros, Dwight Cabrera, Elkim Roa, Wilhelmus A. M. Van Noije:
An improved and automated design tool for the optimization of CMOS OTAs using geometric programming. 146-151 - Pablo Aguirre, Fernando Silveira:
CMOS op-amp power optimization in all regions of inversion using geometric programming. 152-157 - Victor Ariel Leal Sobral, Roberto Espinheira da Costa Bomfim, Robson Nunes de Lima, Ana Isabela Araújo Cunha:
Systematic methodology for the design of Seevinck's CMOS log-domain integrators. 158-163 - Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes:
BenCGen: a digital circuit generation tool for benchmarks. 164-169
Networks-on-chip design and optimization
- Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi:
A simplified executable model to evaluate latency and throughput of networks-on-chip. 170-175 - Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz:
Executable formal specification and validation of NoC communication infrastructures. 176-181 - Fernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans:
MOTIM: an industrial application using nocs. 182-187
FPGA and fault tolerant designs
- Helano Castro, Alexandre Augusto Coelho, Ricardo Jardel Silveira:
Fault-tolerance in FPGA's through CRC voting. 188-192 - Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert:
Evaluating the robustness of secure triple track logic through prototyping. 193-198 - Conrado Pilotto, José Rodrigo Azambuja, Fernanda Lima Kastensmidt:
Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications. 199-204 - Andre Vilas Boas, Eduardo Ribeiro, Alfredo Olmos, Ricardo Maltione:
Self-adaptable slew rate control output buffer for embedded microcontroller port applications. 205-209 - Julien Lallet, Sébastien Pillement, Olivier Sentieys:
Efficient dynamic reconfiguration for multi-context embedded FPGA. 210-215
Advances in image compression architectures
- Marcelo Schiavon Porto, Sergio Bampi, Altamiro Amadeu Susin, Luciano Volcan Agostini:
Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV. 216-221 - Ronaldo Husemann, Altamiro Amadeu Susin, Valter Roesler:
A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filter. 222-227 - Bruno Zatt, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini:
High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV. 228-232 - Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia:
Analog hardware implementation of a vector quantizer for focal-plane image compression. 233-238 - Dieison Antonello Deprá, Vagner Santos Da Rosa, Sergio Bampi:
A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis. 239-244
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