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ORCIDJournal of Electronic Testing, Volume 14
Volume 14, Numbers 1-2, February 1999
- Vishwani D. Agrawal:
Editorial. 7 - Christian Landrault:
Guest Editorial. 11 - Michel Renovell, Florence Azaïs, Yves Bertrand:
Detection of Defects Using Fault Model Oriented Test Sequences. 13-22 - Anna Maria Brosa, Joan Figueras:
Characterization of Floating Gate Defects in Analog Cells. 23-31 - Joop P. M. Van Lammeren:
ICCQ: A Test Method for Analogue VLSI Using Local Current Sensors. 33-38 - Yukiya Miura, Hiroshi Yamazaki:
A Low-Loss Built-In Current Sensor. 39-48 - Frank Poehl, Walter Anheier:
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements. 49-55 - Josep Altet, Antonio Rubio, Wilfrid Claeys, Stefan Dilhaire, Emmanuel Schaub, Hideo Tamamoto:
Differential Thermal Testing: An Approach to its Feasibility. 57-66 - Richard Rosing, Hans G. Kerkhoff, Ronald J. W. T. Tangelder, Manoj Sachdev:
Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters. 67-74 - Nur Engin, Hans G. Kerkhoff, Ronald J. W. T. Tangelder, Han Speek:
Integrated Design and Test of Mixed-Signal Circuits. 75-83 - Gundolf Kiefer, Hans-Joachim Wunderlich:
Deterministic BIST with Multiple Scan Chains. 85-93 - Patrick Girard
, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel:
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. 95-102 - Laurence Tianruo Yang, Zebo Peng:
Incremental Testability Analysis for Partial Scan Selection and Design Transformations. 103-113 - David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
BISTing Datapaths under Heterogeneous Test Schemes. 115-123 - Chris Feige, Jan Ten Pierick, Clemens Wouters, Ronald J. W. T. Tangelder, Hans G. Kerkhoff:
Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach. 125-131 - Ghassan Al Hayek, Chantal Robach:
From Design Validation to Hardware Testing: A Unified Approach. 133-140 - Silvia Chiusano, Fulvio Corno, Paolo Prinetto:
Exploiting Behavioral Information in Gate-Level ATPG. 141-148 - Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira:
Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures. 149-158 - Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGAs: Testing the Embedded RAM Modules. 159-167 - Octavian-Dumitru Mocanu, Joan Oliver:
Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach. 169-180
Volume 14, Number 3, June 1999
- Vishwani D. Agrawal:
Editorial. 187-188 - Rajesh Ramadoss, Michael L. Bushnell:
Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. 189-205 - M. A. El-Gamal, Mohamed Fathy Abu El-Yazeed:
A Combined Clustering and Neural Network Approach for Analog Multiple Hard Fault Classification. 207-217 - Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker:
Testability of 2-Level AND/EXOR Circuits. 219-225 - Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Built-in Self Test Based on Multiple On-Chip Signature Checking. 227-244 - María José López, Mar Martínez, Salvador Bracho:
A Method for Designing a Deterministic Test Pattern Generator Based on Cellular Automata. 245-258 - Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee:
Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits. 259-272 - Yuhai Ma, Wanchun Shi:
Intelligent Analysis and Off-Line Debugging of VLSI Device Test Programs. 273-293 - Vladimir V. Saposhnikov, V. Moshanin, Valerij V. Saposhnikov, Michael Gössel:
Experimental Results for Self-Dual Multi-Output Combinational Circuits. 295-300 - Andreas Rusznyak:
Testing of Oscillators. 301-304 - Janusz A. Brzozowski, Helmut Jürgensen:
Erratum to An Algebra of Multiple Faults in RAMs. 305-306
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