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ORCIDIBM Journal of Research and Development, Volume 24, 1980
Please be aware that the table of contents given here is incomplete.
Volume 24, Number 1, January 1980
- Martin S. Schmokler:
Design of Large ALUs Using Multiple PLA Macros. 2-14 - Edward B. Eichelberger, Eric Lindbloom:
A Heuristic Test-Pattern Generator for Programmable Logic Arrays. 15-22 - Robert L. Golden, Patricia A. Latus, Paul Lowy:
Design Automation and the Programmable Logic Array Macro. 23-31 - Arvind M. Patel:
Error Recovery Scheme for the IBM 3850 Mass Storage System. 32-42 - Peter A. Franaszek:
Synchronous Bounded Delay Coding for Input Restricted Channels. 43-48 - Vijay Ahuja:
Determining Deadlock Exposure for a Class of Store and Forward Communication Networks. 49-55 - Shu Lin, George Markowsky:
On a Class of One-Step Majority-Logic Decodable Cyclic Codes. 56-63 - Michael A. Wesley, Tomás Lozano-Pérez, Lawrence I. Lieberman, Mark A. Lavin, David D. Grossman:
A Geometric Modeling System for Automated Mechanical Assembly. 64-74 - Kin-Man Chung, Fabrizio Luccio, Chak-Kuen Wong:
On the Complexity of Permuting Records in Magnetic Bubble Memory Systems. 75-84
Volume 24, Number 2, March 1980
- Wilhelm Anacker:
Josephson Computer Technology: An IBM Research Project. 107-112 - J. Matisoo:
Overview of Josephson Technology Logic and Memory. 113-129 - T. R. Gheewala:
Design of 2.5-Micrometer Josephson Current Injection Logic (CIL). 130-142 - S. M. Faris, Walter H. Henkels, E. A. Valsamakis, H. H. Zappe:
Basic Design of a Josephson Technology Cache Memory. 143-154 - P. Gueret, A. Moser, P. Wolf:
Investigations for a Josephson Computer Main Memory with Single-Flux-Quantum Cells. 155-166 - Alan V. Brown:
An Overview of Josephson Packaging. 167-171 - Hugh C. Jones, Dennis J. Herrell:
The Characteristics of Chip-to-Chip Signal Propagation in a Package Suitable for Superconducting Circuits. 172-177 - R. F. Broom, W. Kotyczka, A. Moser:
Modeling of Characteristics for Josephson Junctions Having Nonuniform Width or Josephson Current Density. 178-187 - Irving Ames:
An Overview of Materials and Process Aspects of Josephson Integrated Circuit Fabrication. 188-194 - J. H. Greiner, Charles J. Kircher, S. P. Klepner, S. K. Lahiri, A. J. Warnecke, S. Basavaiah, E. T. Yen, John M. Baker, P. R. Brosious, H.-C. W. Huang, M. Murakami, Irving Ames:
Fabrication Process for Josephson Integrated Circuits. 195-205 - R. F. Broom, R. Jaggi, Th. O. Mohr, A. Oosenbrug:
Effect of Process Variables on Electrical Properties of Pb-Alloy Josephson Junctions. 206-211 - R. F. Broom, Robert B. Laibowitz, Th. O. Mohr, W. Walter:
Fabrication and Properties of Niobium Josephson Tunnel Junctions. 212-222 - John M. Baker, Charles J. Kircher, J. W. Matthews:
Structure of Tunnel Barrier Oxide for Pb-Alloy Josephson Junctions. 223-234 - Charles J. Kircher, S. K. Lahiri:
Properties of AuIn2 Resistors for Josephson Integrated Circuits. 235-242 - Frank F. Tsui:
JSP - A Research Signal Processor in Josephson Technology. 243-252
Volume 24, Number 3, May 1980
- S. S. Husson:
Preface. 267 - Richard A. Larsen:
A Silicon and Aluminum Dynamic Memory Technology. 268-282 - Kenneth S. Gray:
Cross-Coupled Charge-Transfer Sense Amplifier and Latch Sense Scheme for High-Density FET Memories. 283-290 - B. F. Fitzgerald, E. P. Thoma:
Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement. 291-298 - Ronald R. Troutman:
VLSI Device Phenomena in Dynamic Memory and Their Application to Technology Development and Device Design. 299-309 - H. J. Geipel, W. K. Tice:
Reduction of Leakage by Implantation Gettering in VLSI Circuits. 310-317 - T. C. Lo, R. E. Scheuerlein, R. Tamlyn:
A 64K FET Dynamic Random Access Memory: Design Considerations and Description. 318-327 - A. Tzou, Y. Gopalakrishna, E. Blaser, O. Bar-Gadda, R. Carballo:
A 256K-Bit Charge-Coupled Device Memory. 328-338 - V. Leo Rideout, John J. Walker, Alice Cramer:
A One-Device Memory Cell Using a Single Layer of Polysilicon and a Self-Registering Metal-to-Polysilicon Contact. 339-347 - L. A. Kasprzak, A. K. Gaind:
Near-Ideal Si-SiO2 Interfaces. 348-352 - D. W. Ormond, J. R. Gardiner:
Reliability of SiO2 Gate Dielectric with Semi-Recessed Oxide Isolation. 353-361 - H. J. Geipel, R. B. Shasteen:
Implanted Source/Drain Junctions for Polysilicon Gate Technologies. 362-369 - Roger L. Verkuil, Huntington W. Curtis, Mun S. Pak:
A Contactless Method for High-Sensitivity Measurement of p-n Junction Leakage. 370-377 - A. Bhattacharyya, D. P. Gaffney, R. A. Kenyon, P. B. Mollier, J. E. Selleck, F. W. Wiedman:
1/N Circuit and Device Technology. 378-389 - Douglas C. Bossen, Mu Y. Hsiao:
A System Solution to the Memory Soft Error Problem. 390-397 - Charles H. Stapper, A. N. McLaren, M. Dreckmann:
Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product. 398-409 - I. T. Ho, J. Riseman, H. Greenhaus:
A Charge Injection Transistor Memory Cell. 410-413
Volume 24, Number 4, July 1980
- D. F. Kyser, R. Pyle:
Computer Simulation of Electron-Beam Resist Profiles. 426-437 - Mihir Parikh:
Proximity Effects in Electron Lithography: Magnitude and Correction Techniques. 438-451 - M. Hatzakis, B. J. Canavello, Jane M. Shaw:
Single-Step Optical Lift-Off Process. 452-460 - H. R. Rottmann:
Overlay in Lithography. 461-468 - Morris Shatzkes, Moshe Av-Ron, Robert A. Gdula:
Defect-Related Breakdown and Conduction in SiO2. 469-479 - Wilm E. Donath:
Stand-Alone Wiring Program for Josephson Logic. 480-485 - Shu Lin, Tadao Kasami, Saburo Yamamura:
Existence of Good δ-Decodable Codes for the Two-User Multiple-Access Adder Channel. 486-495 - John S. Lew:
Optimal Accelerometer Layouts for Data Recovery in Signature Verification. 496-511 - G. G. Adams:
Procedures for the Study of the Flexible-Disk to Head Interface. 512-517
Volume 24, Number 5, September 1980
- Mihir Parikh, Donald E. Schreiber:
Pattern Partitioning for Enhanced Proximity-Effect Corrections in Electron-Beam Lithography. 530-536 - W. D. Grobman, A. J. Speth, T. H. P. Chang:
Proximity Correction Enhancements for 1-µm Dense Circuits. 537-544 - Donald E. Davis:
Registration Mark Detection for Electron-Beam Lithography - EL1 System. 545-553 - J. H. Magerlein, D. J. Webb:
Electron-Beam Resists for Lift-Off Processing with Potential Application to Josephson Integrated Circuits. 554-562 - Yonathan Bard:
Estimation of State Probabilities Using the Maximum Entropy Principle. 563-569 - Philip Heidelberger:
Variance Reduction Techniques for the Simulation of Markov Processes, I: Multiple Estimates. 570-581 - George Markowsky, Michael A. Wesley:
Fleshing Out Wire Frames. 582-597 - J. S. Beeteson, K. T. Jarzebowski, B. R. Sowter:
Digital System for Convergence of Three-Beam High-Resolution Color Data Displays. 598-611 - Bernard Vergnieres:
Macro Generation Algorithms for LSI Custom Chip Design. 612-621 - Ho Chong Lee, Hi Dong Chai:
Integral Point-Matching Method for Two-Dimensional Laplace Field Problems with Periodic Boundaries. 622-630 - Kurt E. Petersen:
Silicon Torsional Scanning Mirror. 631-637 - Peter A. Franaszek:
A General Method for Channel Coding. 638-641
Volume 24, Number 6, November 1980
- Randolph G. Scarborough, Harwood G. Kolsky:
Improved Optimization of FORTRAN Object Programs. 660-676 - Dennis Boyle, Paul Mundy, Thomas M. Spence:
Optimization and Code Generation in a Compiler for Several Machines. 677-683 - Brian L. Marks:
Compilation to Compact Code. 684-691 - John Cocke, Peter W. Markstein:
Communication: Strenght Reduction for Division and Modulo with Application to Accessing a Multilevel Store. 692-694 - Frances E. Allen, J. Lawrence Carter, Janet Fabri, Jeanne Ferrante, William H. Harrison, Paul G. Loewner, Louise Trevillyan:
The Experimental Compiling System. 695-715 - Juan M. Lafuente:
Some Techniques for Compile-Time Analysis of User-Computer Interactions. 716-731 - Norbert J. Denil:
A Business Language. 732-746 - Charles H. Sauer, Edward A. MacNair, Silvio Salza:
A Language for Extended Queuing Network Models. 747-755 - Jose Luis Becerril, Jose Bondia, Ramón Casajuana, Francisco Valer:
Grammar Characterization of Flowgraphs. 756-763 - David B. Lomet:
A Data Definition Facility Based on a Value-Oriented Storage Model. 764-782
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