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ORCIDIET Computers & Digital Techniques, Volume 6
Volume 6, Number 1, January 2012
- Mohammad Hosseinabady
, José Luis Núñez-Yáñez:
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles. 1-11 - Irith Pomeranz:
Test vector chains for increased resolution and reduced storage of diagnostic tests. 12-18 - Srobona Mitra, Priyankar Ghosh, Pallab Dasgupta:
Verification by parts: reusing component invariant checking results. 19-32 - Fei Xia, Andrey Mokhov, Yu Zhou, Yifan Chen, Isi Mitrani, Delong Shang, Danil Sokolov, Alexandre Yakovlev:
Towards power-elastic systems through concurrency management. 33-42 - Tomoyuki Nakabayashi, Takahiro Sasaki, I. K. Ohno, Toshio Kondo:
Design and evaluation of variable stages pipeline processor with low-energy techniques. 43-49 - Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures. 50-58 - Jae Young Hur, Todor P. Stefanov, Stephan Wong, Kees Goossens:
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays. 59-68
Volume 6, Number 2, March 2012
- Samah Mohamed Saeed, Ozgur Sinanoglu:
Multi-modal response compaction adaptive to x-density variation. 69-77 - Irith Pomeranz:
Undetectable transition faults under broadside tests with constant primary input vectors. 78-85 - W.-H. Hu, C.-Y. Chen, Jun Ho Bahn, Nader Bagherzadeh:
Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform. 86-94 - Jasmina Vasiljevic, Andy Gean Ye:
Effect of scaling on the area and performance of the H.264/AVC full-search fractional motion estimation algorithm on field-programmable gate arrays. 95-104 - François Duhem, Fabrice Muller, Philippe Lorenzini:
Reconfiguration time overhead on field programmable gate arrays: reduction and cost model. 105-113 - Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen:
Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip buses. 114-124 - Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Alex Yakovlev:
Design and security evaluation of balanced 1-of-n circuits. 125-135 - Sudarshan K. Srinivasan, Y. Cai, Koushik Sarker:
Refinement-based verification of elastic pipelined systems. 136-152
Volume 6, Number 3, 2012
- Benjamin Carrión Schäfer, Kazutoshi Wakabayashi:
Machine learning predictive modelling high-level synthesis design space exploration. 153-159 - Antonio Lopes Filho, Roberto d'Amore:
Analysis of the error susceptibility of a field programmable gate array-based image compressor through random event injection simulation. 160-165 - Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Evaluation of testability enhancement using software prototype. 166-172 - Abdulaziz Alhussien, Chifeng Wang, Nader Bagherzadeh:
Design and evaluation of a high throughput robust router for network-on-chip. 173-179 - Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi:
Fast inversion algorithm in GF(2m) suitable for implementation with a polynomial multiply instruction on GF(2). 180-185 - Y.-H. Chen, C.-L. Chang, Charles H.-P. Wen:
Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow. 186-193
Volume 6, Number 4, 2012
- Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, Athanasios Milidonis:
Arithmetic module-based built-in self test architecture for two-pattern testing. 195-204 - Arpad Gellert, Horia Calborean, Lucian Vintan, Adrian Florea:
Multi-objective optimisations for a superscalar architecture with selective value prediction. 205-213 - J.-S. Lee, S. Venkateswaran, M. Choi:
Efficient post-configuration testing of an asynchronous nanowire crossbar system for reliability. 214-222 - Irith Pomeranz:
Functional broadside tests for embedded logic blocks. 223-231 - Irith Pomeranz, Sudhakar M. Reddy:
Reset and partial-reset-based functional broadside tests. 232-239 - Saraju P. Mohanty, Elias Kougianos:
Design of experiments and integer linear programming-assisted conjugate-gradient optimisation of high-κ/metal-gate nano-complementary metal-oxide semiconductor static random access memory. 240-248 - Zeljko Jovanovic, Veljko M. Milutinovic:
FPGA accelerator for floating-point matrix multiplication. 249-256
Volume 6, Number 5, 2012
- Ghassem Jaberipur, Behrooz Parhami:
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits. 259-268 - Somayeh Timarchi, Mahmood Fazlali:
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2n - 1, 2n, 2n + 1}. 269-276 - Dongdong Chen, Liu Han, Seok-Bum Ko:
Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture. 277-289 - Nadia Nedjah, Luiza de Macedo Mourelle, Marcos Santana, Sérgio de Souza Raposo:
Massively parallel modular exponentiation method and its implementation in software and hardware for high-performance cryptographic systems. 290-301 - Marjan Asadinia, Mehdi Modarressi, Hamid Sarbazi-Azad:
Supporting non-contiguous processor allocation in mesh-based chip multiprocessors using virtual point-to-point links. 302-317 - Suleyman Tosun, Yilmaz Ar, Suat Ozdemir:
Application-specific topology generation algorithms for network-on-chip design. 318-333 - Sascha Uhrig, Ralf Jahr, Theo Ungerer:
Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor. 334-341 - Mahdi Zare, Shaahin Hessabi, Maziar Goudarzi:
Throughput enhancement for repetitive internal cores in latency-insensitive systems. 342-352
Volume 6, Number 6, 2012
- A. Mitra, Santanu Chattopadhyay:
Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique. 353-361 - Andrew D. Brown, D. J. D. Milton, Andrew J. Rushton, Peter R. Wilson:
Behavioural synthesis utilising recursive definitions. 362-369 - Tomás Lang, Alberto Nannarelli:
Comments on 'improving the speed of decimal division'. 370-371 - Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois:
Asymmetric large size multipliers with optimised FPGA resource utilisation. 372-383 - Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation. 384-395 - Jae Young Hur, Kees Goossens, Lotfi Mhamdi, Muhammad Aqeel Wahlah:
Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays. 396-405 - Ali Valaee, A. J. Al-Khalili:
High-performance low-power sensing scheme for nanoscale SRAMs. 406-413 - Christophe Desmouliers, Erdal Oruklu, Semih Aslan, Jafar Saniie, Fernando Martinez-Vallina:
Image and video processing platform for field programmable gate arrays using a high-level synthesis. 414-425
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