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ORCIDIntegration, Volume 60
Volume 60, January 2018
- Qiang Han, Qiang Xu
, Wen-Ben Jone:
SERA: statistical error rate analysis for profit-oriented performance binning of resilient circuits. 1-12 - M. Kiruba, V. Sumathy:
Register Pre-Allocation based Folded Discrete Tchebichef Transformation Technique for Image Compression. 13-24 - Kunwar Singh, Aman Jain, Aviral Mittal, Vinay Yadav, Atul Anshuman Singh, Anmoll Kumar Jain, Maneesha Gupta:
Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms. 25-38 - Sangmin Kim, Youngsoo Shin:
Module grouping to reduce the area of test wrappers in SoCs. 39-47 - Mohammad Radpour, Sayed Masoud Sayedi:
SystemC-AMS modeling of photodiode based on PWL technique to be used in energy harvesting CMOS image sensor. 48-55 - Minho Nam, Kyoung-Rok Cho:
Implementation of real-time image edge detector based on a bump circuit and active pixels in a CMOS image sensor. 56-62 - Sana Arshad, Rashad Ramzan, Qamar-ul-Wahab:
50-830 MHz noise and distortion canceling CMOS low noise amplifier. 63-73 - Rupam Bhattacharya, Pranab Roy, Hafizur Rahaman:
Homogeneous droplet routing in DMFB: An enhanced technique for high performance bioassay implementation. 74-91 - Yanbin Li, Ming Tang, Yuguang Li, Huanguo Zhang:
Several weaknesses of the implementation for the theoretically secure masking schemes under ISW framework. 92-98 - Hitesh Pahuja, Mintu Tyagi, Sudhakar Panday, Balwinder Singh:
A novel single-ended 9T FinFET sub-threshold SRAM cell with high operating margins and low write power for low voltage operations. 99-116 - Guoyong Shi:
Toward automated reasoning for analog IC design by symbolic computation - A survey. 117-131 - Sheldon X.-D. Tan, Hussam Amrouch, Taeyoung Kim, Zeyu Sun, Chase Cook, Jörg Henkel:
Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited). 132-152 - Urvashi Bansal, Maneesha Gupta:
High bandwidth transimpedance amplifier using FGMOS for low voltage operation. 153-159 - Ahmad Karimi, Abdalhossein Rezai, Mohammad Mahdi Hajhashemkhani:
A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power. 160-166 - Priyajit Mukherjee, Sandeep D'Souza, Santanu Chattopadhyay:
Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution. 167-189 - Ailin Zhang, Guoyong Shi:
A fast symbolic SNR computation method and its Verilog-A implementation for Sigma-Delta modulator design optimization. 190-203 - Austin Lancaster, Manish Keswani:
Integrated circuit packaging review with an emphasis on 3D packaging. 204-212 - Mehmet Tükel, Arda Yurdakul, Berna Örs:
Customizable embedded processor array for multimedia applications. 213-223 - Armineh Arasteh, Mohammad Hossein Moaiyeri, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh:
An energy and area efficient 4: 2 compressor based on FinFETs. 224-231 - Mohsen Hayati, Sajad Cheraghaliei, Sepehr Zarghami:
Design of UWB low noise amplifier using noise-canceling and current-reused techniques. 232-239 - Yiming Ouyang, Jianfeng Yang, Kun Xing, Zhengfeng Huang, Huaguo Liang:
An improved communication scheme for non-HOL-blocking wireless NoC. 240-247 - Jui-Hung Hsieh, Rong-Choi Lee, King-Chu Hung, Meng-Ju Shih:
Rapid and coding-efficient SPIHT algorithm for wavelet-based ECG data compression. 248-256 - Habib Rastegar, Saeid Zare, Jee-Youl Ryu:
A low-voltage low-power capacitive-feedback voltage controlled oscillator. 257-262 - Mohammad Asyaei:
A new low-power dynamic circuit for wide fan-in gates. 263-271 - Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai:
Asymmetry dual-LFSR reseeding for low power BIST. 272-276
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