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ORCIDACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 8
Volume 8, Number 1, January 2003
- Spyros Tragoudas, N. Denny:
Path delay fault testing using test points. 1-10 - Yao-Wen Chang
, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong:
Analysis of FPGA/FPIC switch modules. 11-37 - Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen:
Design theory and implementation for low-power segmented bus systems. 38-54 - Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham:
Floorplan representations: Complexity and connections. 55-80 - Michael A. Riepe, Karem A. Sakallah:
Transistor placement for noncomplementary digital VLSI cell synthesis. 81-107 - Ronald D. Blanton, John P. Hayes:
On the properties of the input pattern fault model. 108-124 - Tanja Van Achteren, Francky Catthoor, Rudy Lauwereins, Geert Deconinck:
Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications. 125-139
Volume 8, Number 2, April 2003
- Stephen A. Edwards:
Tutorial: Compiling concurrent languages for sequential processors. 141-187 - Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang:
Rectilinear block placement using B*-trees. 188-202 - Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang:
Minimum delay optimization for domino circuits - a coupling-aware approach. 202-213 - Ali Pinar, C. L. Liu:
Compacting sequences with invariant transition frequencies. 214-221 - Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton:
Sequential optimization in the absence of global reset. 222-251 - Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai:
Compiler optimization on VLIW instruction scheduling for low power. 252-268
Volume 8, Number 3, July 2003
- Marisa Luisa López-Vallejo, Juan Carlos López:
On the hardware-software partitioning problem: System modeling and partitioning techniques. 269-297 - Stefan Thomas Obenaus, Ted H. Szymanski:
Gravity: Fast placement for 3-D VLSI. 298-315 - Xiaojian Yang, Maogang Wang, Ryan Kastner, Soheil Ghiasi, Majid Sarrafzadeh:
Congestion reduction during placement with provably good approximation bound. 316-333 - George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthesis of saturation arithmetic architectures. 334-354 - Krzysztof Kuchcinski:
Constraints-driven scheduling and resource assignment. 355-383 - Jong-Yeol Lee, In-Cheol Park:
Address code generation for DSP instruction-set architectures. 384-395
Volume 8, Number 4, October 2003
- Shishpal Rawat, Hans-Joachim Wunderlich:
Introduction. 397-398 - Sandeep Kumar Goel, Erik Jan Marinissen:
SOC test architecture design for efficient utilization of test bandwidth. 399-429 - Aiman H. El-Maleh, Yahya E. Osais:
Test vector decomposition-based static compaction algorithms for combinational circuits. 430-459 - Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz:
On test data volume reduction for multiple scan chain designs. 460-469 - Lei Li, Krishnendu Chakrabarty, Nur A. Touba:
Test data compression using dictionaries with selective entries and fixed-length indices. 470-490 - Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan:
Multimode scan: Test per clock BIST for IP cores. 491-505 - Muhammad Nummer, Manoj Sachdev:
Testing high-performance pipelined circuits with slow-speed testers. 506-521 - Kumar L. Parthasarathy, Turker Kuyel, Dana Price, Le Jin, Degang Chen, Randall L. Geiger:
BIST and production testing of ADCs using imprecise stimulus. 522-545 - Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A circuit level fault model for resistive bridges. 546-559 - Dirk Niggemeyer, Elizabeth M. Rudnick:
A data acquisition methodology for on-chip repair of embedded memories. 560-576 - Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro, Ricardo Augusto da Luz Reis:
A multiple bit upset tolerant SRAM memory. 577-590
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