Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Giorgos Dimitrakopoulos
@article{DBLP:journals/cal/PeltekisTND24,
author = {Christodoulos Peltekis and
Vasileios Titopoulos and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {DeMM: {A} Decoupled Matrix Multiplication Engine Supporting Relaxed
Structured Sparsity},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {23},
number = {1},
pages = {17--20},
year = {2024},
url = {https://doi.org/10.1109/LCA.2024.3355178},
doi = {10.1109/LCA.2024.3355178},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/PeltekisTND24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2401-08179,
author = {Christodoulos Peltekis and
Vasileios Titopoulos and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {DeMM: {A} Decoupled Matrix Multiplication Engine Supporting Relaxed
Structured Sparsity},
journal = {CoRR},
volume = {abs/2401.08179},
year = {2024},
url = {https://doi.org/10.48550/arXiv.2401.08179},
doi = {10.48550/ARXIV.2401.08179},
eprinttype = {arXiv},
eprint = {2401.08179},
timestamp = {Thu, 01 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2401-08179.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2402-10118,
author = {Christodoulos Peltekis and
Kosmas Alexandridis and
Giorgos Dimitrakopoulos},
title = {Reusing Softmax Hardware Unit for {GELU} Computation in Transformers},
journal = {CoRR},
volume = {abs/2402.10118},
year = {2024},
url = {https://doi.org/10.48550/arXiv.2402.10118},
doi = {10.48550/ARXIV.2402.10118},
eprinttype = {arXiv},
eprint = {2402.10118},
timestamp = {Mon, 26 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2402-10118.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2402-10850,
author = {Christodoulos Peltekis and
Dionysios Filippas and
Giorgos Dimitrakopoulos},
title = {Error Checking for Sparse Systolic Tensor Arrays},
journal = {CoRR},
volume = {abs/2402.10850},
year = {2024},
url = {https://doi.org/10.48550/arXiv.2402.10850},
doi = {10.48550/ARXIV.2402.10850},
eprinttype = {arXiv},
eprint = {2402.10850},
timestamp = {Mon, 26 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2402-10850.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/PeltekisFDN23,
author = {Christodoulos Peltekis and
Dionysios Filippas and
Giorgos Dimitrakopoulos and
Chrysostomos Nicopoulos},
title = {Exploiting data encoding and reordering for low-power streaming in
systolic arrays},
journal = {Microprocess. Microsystems},
volume = {102},
pages = {104938},
year = {2023},
url = {https://doi.org/10.1016/j.micpro.2023.104938},
doi = {10.1016/J.MICPRO.2023.104938},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/PeltekisFDN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MangirasCD23,
author = {Dimitrios Mangiras and
David G. Chinnery and
Giorgos Dimitrakopoulos},
title = {Task-Based Parallel Programming for Gate Sizing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {4},
pages = {1309--1322},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3197490},
doi = {10.1109/TCAD.2022.3197490},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MangirasCD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FilippasND23,
author = {Dionysios Filippas and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Streaming Dilated Convolution Engine},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {401--405},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3233882},
doi = {10.1109/TVLSI.2022.3233882},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FilippasND23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/StefanidisZFDS23,
author = {Apostolos Stefanidis and
Ioanna Zoumpoulidou and
Dionysios Filippas and
Giorgos Dimitrakopoulos and
Georgios Ch. Sirakoulis},
title = {Synthesis of Approximate Parallel-Prefix Adders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1686--1699},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3287631},
doi = {10.1109/TVLSI.2023.3287631},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/StefanidisZFDS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/FilippasPDN23,
author = {Dionysios Filippas and
Christodoulos Peltekis and
Giorgos Dimitrakopoulos and
Chrysostomos Nicopoulos},
title = {Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with
Skewed Pipelines},
booktitle = {5th {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2023, Hangzhou, China, June 11-13, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/AICAS57966.2023.10168556},
doi = {10.1109/AICAS57966.2023.10168556},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aicas/FilippasPDN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PeltekisFDNP23,
author = {Christodoulos Peltekis and
Dionysios Filippas and
Giorgos Dimitrakopoulos and
Chrysostomos Nicopoulos and
Dionisios N. Pnevmatikatos},
title = {ArrayFlex: {A} Systolic Array Architecture with Configurable Transparent
Pipelining},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10136913},
doi = {10.23919/DATE56975.2023.10136913},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PeltekisFDNP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/DimitrakopoulosKTSN23,
author = {Giorgos Dimitrakopoulos and
E. Kallitsounakis and
Z. Takakis and
A. Stefanidis and
Chrysostomos Nicopoulos},
title = {Multi-Armed Bandits for Autonomous Test Application in {RISC-V} Processor
Verification},
booktitle = {12th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2023, Athens, Greece, June 28-30, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MOCAST57943.2023.10176659},
doi = {10.1109/MOCAST57943.2023.10176659},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mocast/DimitrakopoulosKTSN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/PeltekisFDN23,
author = {Christodoulos Peltekis and
Dionysios Filippas and
Giorgos Dimitrakopoulos and
Chrysostomos Nicopoulos},
title = {Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding
and Zero-Value Clock Gating},
booktitle = {12th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2023, Athens, Greece, June 28-30, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MOCAST57943.2023.10176467},
doi = {10.1109/MOCAST57943.2023.10176467},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mocast/PeltekisFDN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2304-01668,
author = {Dionysios Filippas and
Christodoulos Peltekis and
Giorgos Dimitrakopoulos and
Chrysostomos Nicopoulos},
title = {Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with
Skewed Pipelines},
journal = {CoRR},
volume = {abs/2304.01668},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2304.01668},
doi = {10.48550/ARXIV.2304.01668},
eprinttype = {arXiv},
eprint = {2304.01668},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2304-01668.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2304-12691,
author = {Christodoulos Peltekis and
Dionysios Filippas and
Giorgos Dimitrakopoulos and
Chrysostomos Nicopoulos},
title = {Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding
and Zero-Value Clock Gating},
journal = {CoRR},
volume = {abs/2304.12691},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2304.12691},
doi = {10.48550/ARXIV.2304.12691},
eprinttype = {arXiv},
eprint = {2304.12691},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2304-12691.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2309-02969,
author = {Christodoulos Peltekis and
Dionysios Filippas and
Giorgos Dimitrakopoulos and
Chrysostomos A. Nicopoulos},
title = {The Case for Asymmetric Systolic Array Floorplanning},
journal = {CoRR},
volume = {abs/2309.02969},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2309.02969},
doi = {10.48550/ARXIV.2309.02969},
eprinttype = {arXiv},
eprint = {2309.02969},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2309-02969.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2311-07241,
author = {Vasileios Titopoulos and
K. Alexandridis and
Christodoulos Peltekis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {IndexMAC: {A} Custom {RISC-V} Vector Instruction to Accelerate Structured-Sparse
Matrix Multiplications},
journal = {CoRR},
volume = {abs/2311.07241},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2311.07241},
doi = {10.48550/ARXIV.2311.07241},
eprinttype = {arXiv},
eprint = {2311.07241},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2311-07241.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FilippasMMND22,
author = {Dionysios Filippas and
Nikolaos Margomenos and
Nikolaos Mitianoudis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Low-Cost Online Convolution Checksum Checker},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {201--212},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3119511},
doi = {10.1109/TVLSI.2021.3119511},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FilippasMMND22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/PeltekisFND22,
author = {Christodoulos Peltekis and
Dionysios Filippas and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {FusedGCN: {A} Systolic Three-Matrix Multiplication Architecture for
Graph Convolutional Networks},
booktitle = {33rd {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2022, Gothenburg, Sweden, July
12-14, 2022},
pages = {93--97},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASAP54787.2022.00024},
doi = {10.1109/ASAP54787.2022.00024},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/PeltekisFND22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/FilippasND22,
author = {Dionysios Filippas and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable
Stride},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2022, Nicosia,
Cyprus, July 4-6, 2022},
pages = {200--205},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISVLSI54635.2022.00047},
doi = {10.1109/ISVLSI54635.2022.00047},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/FilippasND22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/SazeidesGGB0GND22,
author = {Yiannakis Sazeides and
Alex Gerber and
Ron Gabor and
Arkady Bramnik and
George Papadimitriou and
Dimitris Gizopoulos and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos and
Karyofyllis Patsidis},
title = {{IDLD:} Instantaneous Detection of Leakage and Duplication of Identifiers
used for Register Renaming},
booktitle = {55th {IEEE/ACM} International Symposium on Microarchitecture, {MICRO}
2022, Chicago, IL, USA, October 1-5, 2022},
pages = {799--814},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MICRO56248.2022.00061},
doi = {10.1109/MICRO56248.2022.00061},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/SazeidesGGB0GND22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/Dimitrakopoulos22,
author = {Giorgos Dimitrakopoulos and
Anastasios Psarras and
Chrysostomos Nicopoulos},
title = {Virtual-Channel Flow Control Across Mesochronous Clock Domains},
booktitle = {11th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2022, Bremen, Germany, June 8-10, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MOCAST54814.2022.9837772},
doi = {10.1109/MOCAST54814.2022.9837772},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mocast/Dimitrakopoulos22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2211-12600,
author = {Christodoulos Peltekis and
Dionysios Filippas and
Giorgos Dimitrakopoulos and
Chrysostomos Nicopoulos and
Dionisios N. Pnevmatikatos},
title = {ArrayFlex: {A} Systolic Array Architecture with Configurable Transparent
Pipelining},
journal = {CoRR},
volume = {abs/2211.12600},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2211.12600},
doi = {10.48550/ARXIV.2211.12600},
eprinttype = {arXiv},
eprint = {2211.12600},
timestamp = {Tue, 29 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2211-12600.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KonstantinouNLD21,
author = {Dimitris Konstantinou and
Chrysostomos Nicopoulos and
Junghee Lee and
Giorgos Dimitrakopoulos},
title = {Multicast-enabled network-on-chip routers leveraging partitioned allocation
and switching},
journal = {Integr.},
volume = {77},
pages = {104--112},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.10.008},
doi = {10.1016/J.VLSI.2020.10.008},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KonstantinouNLD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StefanidisMNCD21,
author = {Apostolos Stefanidis and
Dimitrios Mangiras and
Chrysostomos Nicopoulos and
David G. Chinnery and
Giorgos Dimitrakopoulos},
title = {Autonomous Application of Netlist Transformations Inside Lagrangian
Relaxation-Based Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {8},
pages = {1672--1686},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3025541},
doi = {10.1109/TCAD.2020.3025541},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StefanidisMNCD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tetc/Dimitrakopoulos21,
author = {Giorgos Dimitrakopoulos and
Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {Sum Propagate Adders},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {9},
number = {3},
pages = {1479--1488},
year = {2021},
url = {https://doi.org/10.1109/TETC.2021.3068729},
doi = {10.1109/TETC.2021.3068729},
timestamp = {Tue, 05 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tetc/Dimitrakopoulos21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/Dimitrakopoulos21,
author = {Giorgos Dimitrakopoulos and
Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {Sum Propagate Adders},
booktitle = {28th {IEEE} Symposium on Computer Arithmetic, {ARITH} 2021, Lyngby,
Denmark, June 14-16, 2021},
pages = {110},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ARITH51176.2021.00030},
doi = {10.1109/ARITH51176.2021.00030},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/Dimitrakopoulos21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/MangirasD21,
author = {Dimitrios Mangiras and
Giorgos Dimitrakopoulos},
title = {Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold
Voltage Assignment},
booktitle = {10th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2021, Thessaloniki, Greece, July 5-7, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MOCAST52088.2021.9493338},
doi = {10.1109/MOCAST52088.2021.9493338},
timestamp = {Mon, 02 Aug 2021 16:38:24 +0200},
biburl = {https://dblp.org/rec/conf/mocast/MangirasD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MangirasSSND20,
author = {Dimitrios Mangiras and
Apostolos Stefanidis and
Ioannis Seitanidis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Timing-Driven Placement Optimization Facilitated by Timing-Compatibility
Flip-Flop Clustering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {10},
pages = {2835--2848},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2942001},
doi = {10.1109/TCAD.2019.2942001},
timestamp = {Tue, 06 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MangirasSSND20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KonstantinouPND20,
author = {Dimitrios Konstantinou and
Anastasios Psarras and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {The Mesochronous Dual-Clock {FIFO} Buffer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {302--306},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2946348},
doi = {10.1109/TVLSI.2019.2946348},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KonstantinouPND20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/SazeidesBGNCKD20,
author = {Yiannakis Sazeides and
Arkady Bramnik and
Ron Gabor and
Chrysostomos Nicopoulos and
Ramon Canal and
Dimitris Konstantinou and
Giorgos Dimitrakopoulos},
editor = {Luigi Dilillo and
Mihalis Psarakis and
Taniya Siddiqua},
title = {2D Error Correction for {F/F} based Arrays using In-Situ Real-Time
Error Detection {(RTD)}},
booktitle = {{IEEE} International Symposium on Defect and Fault Tolerance in {VLSI}
and Nanotechnology Systems, {DFT} 2020, Frascati, Italy, October 19-21,
2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DFT50435.2020.9250878},
doi = {10.1109/DFT50435.2020.9250878},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/SazeidesBGNCKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChatzinikolaouF20,
author = {Theodoros Panagiotis Chatzinikolaou and
Iosif{-}Angelos Fyrigos and
Rafailia{-}Eleni Karamani and
Vasileios G. Ntinas and
Giorgos Dimitrakopoulos and
Sorin Cotofana and
Georgios Ch. Sirakoulis},
title = {Memristive Oscillatory Circuits for Resolution of NP-Complete Logic
Puzzles: Sudoku Case},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9181110},
doi = {10.1109/ISCAS45731.2020.9181110},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChatzinikolaouF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KonstantinouNLS20,
author = {Dimitrios Konstantinou and
Chrysostomos Nicopoulos and
Junghee Lee and
Georgios Ch. Sirakoulis and
Giorgos Dimitrakopoulos},
title = {SmartFork: Partitioned Multicast Allocation and Switching in Network-on-Chip
Routers},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180774},
doi = {10.1109/ISCAS45731.2020.9180774},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KonstantinouNLS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PatsidisNSD20,
author = {Karyofyllis Patsidis and
Chrysostomos Nicopoulos and
Georgios Ch. Sirakoulis and
Giorgos Dimitrakopoulos},
title = {{RISC-V2:} {A} Scalable {RISC-V} Vector Processor},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9181071},
doi = {10.1109/ISCAS45731.2020.9181071},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/PatsidisNSD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/MangirasMRD20,
author = {Dimitrios Mangiras and
Pavlos M. Mattheakis and
Pierre{-}Olivier Ribet and
Giorgos Dimitrakopoulos},
editor = {William Swartz and
Jens Lienig},
title = {Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced
{OCV}},
booktitle = {{ISPD} 2020: International Symposium on Physical Design, Taipei, Taiwan,
March 29 - April 1, 2020, delayed to September 20-23, 2020},
pages = {25--32},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3372780.3375564},
doi = {10.1145/3372780.3375564},
timestamp = {Sun, 22 Mar 2020 19:04:23 +0100},
biburl = {https://dblp.org/rec/conf/ispd/MangirasMRD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/StefanidisMNCD20,
author = {Apostolos Stefanidis and
Dimitrios Mangiras and
Chrysostomos Nicopoulos and
David G. Chinnery and
Giorgos Dimitrakopoulos},
editor = {William Swartz and
Jens Lienig},
title = {Design Optimization by Fine-grained Interleaving of Local Netlist
Transformations in Lagrangian Relaxation},
booktitle = {{ISPD} 2020: International Symposium on Physical Design, Taipei, Taiwan,
March 29 - April 1, 2020, delayed to September 20-23, 2020},
pages = {87--94},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3372780.3375566},
doi = {10.1145/3372780.3375566},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/StefanidisMNCD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/KaramaniFNLDAAS20,
author = {Rafailia{-}Eleni Karamani and
Iosif{-}Angelos Fyrigos and
Vasileios G. Ntinas and
Orestis Liolis and
Giorgos Dimitrakopoulos and
Mustafa Altun and
Andrew Adamatzky and
Mircea R. Stan and
Georgios Ch. Sirakoulis},
title = {Memristive Learning Cellular Automata: Theory and Applications},
booktitle = {9th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2020, Bremen, Germany, September 7-9, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MOCAST49295.2020.9200246},
doi = {10.1109/MOCAST49295.2020.9200246},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mocast/KaramaniFNLDAAS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2002-06339,
author = {Theodoros Panagiotis Chatzinikolaou and
Iosif{-}Angelos Fyrigos and
Rafailia{-}Eleni Karamani and
Vasileios G. Ntinas and
Giorgos Dimitrakopoulos and
Sorin Cotofana and
Georgios Ch. Sirakoulis},
title = {Memristive oscillatory circuits for resolution of NP-complete logic
puzzles: Sudoku case},
journal = {CoRR},
volume = {abs/2002.06339},
year = {2020},
url = {https://arxiv.org/abs/2002.06339},
eprinttype = {arXiv},
eprint = {2002.06339},
timestamp = {Mon, 02 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2002-06339.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2003-06983,
author = {Rafailia{-}Eleni Karamani and
Iosif{-}Angelos Fyrigos and
Vasileios G. Ntinas and
Orestis Liolis and
Giorgos Dimitrakopoulos and
Mustafa Altun and
Andrew Adamatzky and
Mircea R. Stan and
Georgios Ch. Sirakoulis},
title = {Memristive Learning Cellular Automata: Theory and Applications},
journal = {CoRR},
volume = {abs/2003.06983},
year = {2020},
url = {https://arxiv.org/abs/2003.06983},
eprinttype = {arXiv},
eprint = {2003.06983},
timestamp = {Tue, 17 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2003-06983.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeitanidisND19,
author = {Ioannis Seitanidis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Automatic Generation of Peak-Power Traffic for Networks-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {96--108},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2801223},
doi = {10.1109/TCAD.2018.2801223},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SeitanidisND19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeitanidisDMMC19,
author = {Ioannis Seitanidis and
Giorgos Dimitrakopoulos and
Pavlos M. Mattheakis and
Laurent Masse{-}Navette and
David G. Chinnery},
title = {Timing-Driven and Placement-Aware Multibit Register Composition},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1501--1514},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2852740},
doi = {10.1109/TCAD.2018.2852740},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeitanidisDMMC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GaborSBANPKD19,
author = {Ron Gabor and
Yiannakis Sazeides and
Arkady Bramnik and
Alexandros Andreou and
Chrysostomos Nicopoulos and
Karyofyllis Patsidis and
Dimitris Konstantinou and
Giorgos Dimitrakopoulos},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled
Out-of-Order Core},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {812--817},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8715194},
doi = {10.23919/DATE.2019.8715194},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GaborSBANPKD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ivsw/TakakisMND19,
author = {Zacharias Takakis and
Dimitrios Mangiras and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional
Coverage},
booktitle = {4th {IEEE} International Verification and Security Workshop, {IVSW}
2019, Rhodes Island, Greece, July 1-3, 2019},
pages = {61--66},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/IVSW.2019.8854389},
doi = {10.1109/IVSW.2019.8854389},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ivsw/TakakisMND19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/StefanidisMND19,
author = {Apostolos Stefanidis and
Dimitrios Mangiras and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Multi-Armed Bandits for Autonomous Timing-driven Design Optimization},
booktitle = {29th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2019, Rhodes, Greece, July 1-3, 2019},
pages = {17--22},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/PATMOS.2019.8862056},
doi = {10.1109/PATMOS.2019.8862056},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/StefanidisMND19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/PatsidisKND18,
author = {Karyofyllis Patsidis and
Dimitris Konstantinou and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {A low-cost synthesizable {RISC-V} dual-issue processor core leveraging
the compressed Instruction Set Extension},
journal = {Microprocess. Microsystems},
volume = {61},
pages = {1--10},
year = {2018},
url = {https://doi.org/10.1016/j.micpro.2018.05.007},
doi = {10.1016/J.MICPRO.2018.05.007},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/PatsidisKND18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/KonstantinouPDN18,
author = {Dimitris Konstantinou and
Anastasios Psarras and
Giorgos Dimitrakopoulos and
Chrysostomos Nicopoulos},
title = {Low-power dual-edge-triggered synchronous latency-insensitive systems},
booktitle = {7th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2018, Thessaloniki, Greece, May 7-9, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MOCAST.2018.8376625},
doi = {10.1109/MOCAST.2018.8376625},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mocast/KonstantinouPDN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/KarampasisPVLPB17,
author = {Emmanuel Karampasis and
Nick P. Papanikolaou and
Dionisis Voglitsis and
Michael Loupis and
Anastasios Psarras and
Alexandros Boubaris and
Dimitris Baros and
Giorgos Dimitrakopoulos},
title = {Active Thermoelectric Cooling Solutions for Airspace Applications:
the {THERMICOOL} Project},
journal = {{IEEE} Access},
volume = {5},
pages = {2288--2299},
year = {2017},
url = {https://doi.org/10.1109/ACCESS.2017.2672818},
doi = {10.1109/ACCESS.2017.2672818},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/KarampasisPVLPB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PsarrasPND17,
author = {Anastasios Psarras and
Michalis Paschou and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {A Dual-Clock Multiple-Queue Shared Buffer},
journal = {{IEEE} Trans. Computers},
volume = {66},
number = {10},
pages = {1809--1815},
year = {2017},
url = {https://doi.org/10.1109/TC.2017.2705141},
doi = {10.1109/TC.2017.2705141},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/PsarrasPND17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/PsarrasMND17,
author = {Anastasios Psarras and
Savvas Moisidis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Networks-on-Chip With Double-Data-Rate Links},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {64-I},
number = {12},
pages = {3103--3114},
year = {2017},
url = {https://doi.org/10.1109/TCSI.2017.2734689},
doi = {10.1109/TCSI.2017.2734689},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/PsarrasMND17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SeitanidisDMMC17,
author = {Ioannis Seitanidis and
Giorgos Dimitrakopoulos and
Pavlos M. Mattheakis and
Laurent Masse{-}Navette and
David G. Chinnery},
title = {Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware
{ILP} formulation},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {56:1--56:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062327},
doi = {10.1145/3061639.3062327},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/SeitanidisDMMC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DebnathKNDLL17,
author = {Monobrata Debnath and
Dimitris Konstantinou and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos and
Wei{-}Ming Lin and
Junghee Lee},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Low-cost congestion management in networks-on-chip using edge and
in-network traffic throttling},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {8--11},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073764},
doi = {10.1145/3073763.3073764},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/DebnathKNDLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/ChrysanthouEPPN16,
author = {Kypros Chrysanthou and
Panayiotis Englezakis and
Andreas Prodromou and
Andreas Panteli and
Chrysostomos Nicopoulos and
Yiannakis Sazeides and
Giorgos Dimitrakopoulos},
title = {An Online and Real-Time Fault Detection and Localization Mechanism
for Network-on-Chip Architectures},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {13},
number = {2},
pages = {22:1--22:26},
year = {2016},
url = {https://doi.org/10.1145/2930670},
doi = {10.1145/2930670},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/ChrysanthouEPPN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PsarrasSND16,
author = {Anastasios Psarras and
Ioannis Seitanidis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {ShortPath: {A} Network-on-Chip Router with Fine-Grained Pipeline Bypassing},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {10},
pages = {3136--3147},
year = {2016},
url = {https://doi.org/10.1109/TC.2016.2519916},
doi = {10.1109/TC.2016.2519916},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/PsarrasSND16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PsarrasLSND16,
author = {Anastasios Psarras and
Junghee Lee and
Ioannis Seitanidis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled
Virtual Channels},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {5},
pages = {844--857},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2015.2488490},
doi = {10.1109/TCAD.2015.2488490},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/PsarrasLSND16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PaschouPND16,
author = {Michalis Paschou and
Anastasios Psarras and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {CrossOver: Clock domain crossing under virtual-channel flow control},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {1183--1188},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459491/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/PaschouPND16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PsarrasLMND16,
author = {Anastasios Psarras and
Junghee Lee and
Pavlos M. Mattheakis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
editor = {Ayse K. Coskun and
Martin Margala and
Laleh Behjat and
Jie Han},
title = {A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors},
booktitle = {Proceedings of the 26th edition on Great Lakes Symposium on VLSI,
{GLVLSI} 2016, Boston, MA, USA, May 18-20, 2016},
pages = {335--340},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2902961.2903010},
doi = {10.1145/2902961.2903010},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PsarrasLMND16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PsarrasMND16,
author = {Anastasios Psarras and
Savvas Moisidis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {RapidLink: {A} network-on-chip architecture with double-data-rate
links},
booktitle = {2016 {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2016, Monte Carlo, Monaco, December 11-14, 2016},
pages = {93--96},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ICECS.2016.7841140},
doi = {10.1109/ICECS.2016.7841140},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/PsarrasMND16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/SeitanidisND16,
author = {Ioannis Seitanidis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Powermax: an automated methodology for generating peak-power traffic
in networks-on-chip},
booktitle = {Tenth {IEEE/ACM} International Symposium on Networks-on-Chip, {NOCS}
2016, Nara, Japan, August 31 - September 2, 2016},
pages = {1--8},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/NOCS.2016.7579318},
doi = {10.1109/NOCS.2016.7579318},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/SeitanidisND16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2016aistecs,
editor = {S{\"{o}}ren Sonntag and
Sandro Bartolini and
Giorgos Dimitrakopoulos and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {Proceedings of the 1st International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2016, Prague, Czech Republic, January 18, 2016},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857058},
doi = {10.1145/2857058},
isbn = {978-1-4503-4084-7},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2016aistecs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/BertozziDFS15,
author = {Davide Bertozzi and
Giorgos Dimitrakopoulos and
Jos{\'{e}} Flich and
S{\"{o}}ren Sonntag},
title = {The fast evolving landscape of on-chip communication - Selected future
challenges and research avenues},
journal = {Des. Autom. Embed. Syst.},
volume = {19},
number = {1-2},
pages = {59--76},
year = {2015},
url = {https://doi.org/10.1007/s10617-014-9137-6},
doi = {10.1007/S10617-014-9137-6},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dafes/BertozziDFS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeitanidisPCND15,
author = {Ioannis Seitanidis and
Anastasios Psarras and
Kypros Chrysanthou and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based
Networks on Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {12},
pages = {3015--3028},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2383442},
doi = {10.1109/TVLSI.2014.2383442},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeitanidisPCND15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PsarrasSND15,
author = {Anastasios Psarras and
I. Seitanidis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
editor = {Wolfgang Nebel and
David Atienza},
title = {PhaseNoC: {TDM} scheduling at the virtual-channel level for efficient
network traffic isolation},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {1090--1095},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2757066},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/PsarrasSND15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/PanteloukasPND15,
author = {Alexandros Panteloukas and
Anastasios Psarras and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Timing-resilient Network-on-Chip architectures},
booktitle = {21st {IEEE} International On-Line Testing Symposium, {IOLTS} 2015,
Halkidiki, Greece, July 6-8, 2015},
pages = {77--82},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/IOLTS.2015.7229836},
doi = {10.1109/IOLTS.2015.7229836},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/iolts/PanteloukasPND15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/BertozziDS14,
author = {Davide Bertozzi and
Giorgos Dimitrakopoulos and
S{\"{o}}ren Sonntag},
title = {Editorial},
journal = {Des. Autom. Embed. Syst.},
volume = {18},
number = {3-4},
pages = {119--120},
year = {2014},
url = {https://doi.org/10.1007/s10617-014-9136-7},
doi = {10.1007/S10617-014-9136-7},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/BertozziDS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DimitrakopoulosSPTMC14,
author = {Giorgos Dimitrakopoulos and
I. Seitanidis and
Anastasios Psarras and
K. Tsiouris and
Pavlos M. Mattheakis and
Jordi Cortadella},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Hardware primitives for the synthesis of multithreaded elastic systems},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--4},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.314},
doi = {10.7873/DATE.2014.314},
timestamp = {Thu, 25 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/DimitrakopoulosSPTMC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SeitanidisPDN14,
author = {I. Seitanidis and
Anastasios Psarras and
Giorgos Dimitrakopoulos and
Chrysostomos Nicopoulos},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {ElastiStore: An elastic buffer architecture for Network-on-Chip routers},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--6},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.253},
doi = {10.7873/DATE.2014.253},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/SeitanidisPDN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/SeitanidisPKND14,
author = {I. Seitanidis and
Anastasios Psarras and
Emmanouil Kalligeros and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
editor = {Davide Bertozzi and
Luca Benini and
Sudhakar Yalamanchili and
J{\"{o}}rg Henkel},
title = {ElastiNoC: {A} self-testable distributed VC-based Network-on-Chip
architecture},
booktitle = {Eighth {IEEE/ACM} International Symposium on Networks-on-Chip, NoCS
2014, Ferrara, Italy, September 17-19, 2014},
pages = {135--142},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/NOCS.2014.7008772},
doi = {10.1109/NOCS.2014.7008772},
timestamp = {Wed, 16 Oct 2019 14:14:48 +0200},
biburl = {https://dblp.org/rec/conf/nocs/SeitanidisPKND14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2014ina-ocmc,
editor = {Giorgos Dimitrakopoulos and
S{\"{o}}ren Sonntag and
Jos{\'{e}} Flich and
Pascal Vivet},
title = {Proceedings of the 8th International Workshop on Interconnection Network
Architecture - On-Chip, Multi-Chip, {INA-OCMC} 2014, Vienna, Austria,
January 22, 2014},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556857},
doi = {10.1145/2556857},
isbn = {978-1-4503-2639-1},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2014ina-ocmc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2014nocarc,
editor = {Farhad Mehdipour and
Giorgos Dimitrakopoulos},
title = {Proceedings of the 2014 International Workshop on Network on Chip
Architectures, NoCArc '14, Cambridge, United Kingdom, December 13-14,
2014},
publisher = {{ACM}},
year = {2014},
url = {http://dl.acm.org/citation.cfm?id=2685342},
isbn = {978-1-4503-3064-0},
timestamp = {Sun, 15 Mar 2015 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/2014nocarc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/DimitrakopoulosKG13,
author = {Giorgos Dimitrakopoulos and
Emmanouil Kalligeros and
Costas Galanopoulos},
title = {Merged Switch Allocation and Traversal in Network-on-Chip Switches},
journal = {{IEEE} Trans. Computers},
volume = {62},
number = {10},
pages = {2001--2012},
year = {2013},
url = {https://doi.org/10.1109/TC.2012.116},
doi = {10.1109/TC.2012.116},
timestamp = {Wed, 14 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/DimitrakopoulosKG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DimitrakopoulosGNK13,
author = {Giorgos Dimitrakopoulos and
N. Georgiadis and
Chrysostomos Nicopoulos and
Emmanouil Kalligeros},
editor = {Enrico Macii},
title = {Switch folding: network-on-chip routers with time-multiplexed output
ports},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {344--349},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.081},
doi = {10.7873/DATE.2013.081},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/DimitrakopoulosGNK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/VergosD12,
author = {Haridimos T. Vergos and
Giorgos Dimitrakopoulos},
title = {On Modulo 2{\^{}}n+1 Adder Design},
journal = {{IEEE} Trans. Computers},
volume = {61},
number = {2},
pages = {173--186},
year = {2012},
url = {https://doi.org/10.1109/TC.2010.261},
doi = {10.1109/TC.2010.261},
timestamp = {Wed, 14 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/VergosD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GraciaDAKY12,
author = {Dar{\'{\i}}o Su{\'{a}}rez Gracia and
Giorgos Dimitrakopoulos and
Teresa Monreal Arnal and
Manolis Katevenis and
V{\'{\i}}ctor Vi{\~{n}}als Y{\'{u}}fera},
title = {{LP-NUCA:} Networks-in-Cache for High-Performance Low-Power Embedded
Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1510--1523},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2158249},
doi = {10.1109/TVLSI.2011.2158249},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GraciaDAKY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DimitrakopoulosK12,
author = {Giorgos Dimitrakopoulos and
Emmanouil Kalligeros},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {Dynamic-priority arbiter and multiplexer soft macros for on-chip networks
switches},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {542--545},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176527},
doi = {10.1109/DATE.2012.6176527},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/DimitrakopoulosK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/RocaFD12,
author = {Antoni Roca and
Jos{\'{e}} Flich and
Giorgos Dimitrakopoulos},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {{DESA:} Distributed Elastic Switch Architecture for efficient networks-on-FPGAS},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {394--399},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339135},
doi = {10.1109/FPL.2012.6339135},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/RocaFD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Dimitrakopoulos12,
author = {Giorgos Dimitrakopoulos and
Emmanouil Kalligeros},
title = {Low-cost fault-tolerant switch allocator for network-on-chip routers},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {25--28},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107770},
doi = {10.1145/2107763.2107770},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Dimitrakopoulos12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/DimitrakopoulosKK11,
author = {Giorgos Dimitrakopoulos and
Christoforos Kachris and
Emmanouil Kalligeros},
title = {Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2011, September 5-7, Chania, Crete, Greece},
pages = {90--96},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/FPL.2011.26},
doi = {10.1109/FPL.2011.26},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/DimitrakopoulosKK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Dimitrakopoulos11,
author = {Giorgos Dimitrakopoulos and
Kostas Galanopoulos},
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {Switch allocator for bufferless network-on-chip routers},
booktitle = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
pages = {19--22},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037.1930043},
doi = {10.1145/1930037.1930043},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Dimitrakopoulos11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/ChrysosD09,
author = {Nikos Chrysos and
Giorgos Dimitrakopoulos},
title = {Practical High-Throughput Crossbar Scheduling},
journal = {{IEEE} Micro},
volume = {29},
number = {4},
pages = {22--35},
year = {2009},
url = {https://doi.org/10.1109/MM.2009.71},
doi = {10.1109/MM.2009.71},
timestamp = {Wed, 14 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/ChrysosD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tele/KritikouDDD09,
author = {Yiouli Kritikou and
Giorgos Dimitrakopoulos and
E. Dimitrellou and
Panagiotis Demestichas},
title = {A management scheme for improving transportation efficiency and contributing
to the enhancement of the social fabric},
journal = {Telematics Informatics},
volume = {26},
number = {4},
pages = {375--390},
year = {2009},
url = {https://doi.org/10.1016/j.tele.2008.10.002},
doi = {10.1016/J.TELE.2008.10.002},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tele/KritikouDDD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DimitrakopoulosGMN08,
author = {Giorgos Dimitrakopoulos and
Costas Galanopoulos and
Christos Mavrokefalidis and
Dimitris Nikolos},
title = {Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed
Floating Point Units},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {7},
pages = {837--850},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2000458},
doi = {10.1109/TVLSI.2008.2000458},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DimitrakopoulosGMN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hoti/ChrysosD08,
author = {Nikos Chrysos and
Giorgos Dimitrakopoulos},
title = {Backlog-Aware Crossbar Schedulers: {A} New Algorithm and its Efficient
Hardware Implementation},
booktitle = {16th Annual {IEEE} Symposium on High Performance Interconnects {(HOTI}
2008), 26-28 August 2008, Stanford, CA, {USA}},
pages = {67--74},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/HOTI.2008.18},
doi = {10.1109/HOTI.2008.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hoti/ChrysosD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/DimitrakopoulosCG08,
author = {Giorgos Dimitrakopoulos and
Nikos Chrysos and
Costas Galanopoulos},
title = {Fast arbiters for on-chip network switches},
booktitle = {26th International Conference on Computer Design, {ICCD} 2008, 12-15
October 2008, Lake Tahoe, CA, USA, Proceedings},
pages = {664--670},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCD.2008.4751932},
doi = {10.1109/ICCD.2008.4751932},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/DimitrakopoulosCG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DimitrakopoulosMGN07,
author = {Giorgos Dimitrakopoulos and
Christos Mavrokefalidis and
Costas Galanopoulos and
Dimitris Nikolos},
title = {Sorter Based Permutation Units for Media-Enhanced Microprocessors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {15},
number = {6},
pages = {711--715},
year = {2007},
url = {https://doi.org/10.1109/TVLSI.2007.898750},
doi = {10.1109/TVLSI.2007.898750},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DimitrakopoulosMGN07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/DimitrakopoulosMGN06,
author = {Giorgos Dimitrakopoulos and
Christos Mavrokefalidis and
Costas Galanopoulos and
Dimitris Nikolos},
title = {An Energy-Delay Efficient Subword Permutation Unit},
booktitle = {2006 {IEEE} International Conference on Application-Specific Systems,
Architecture and Processors {(ASAP} 2006), 11-13 September 2006, Steamboat
Springs, Colorado, {USA}},
pages = {245--252},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ASAP.2006.10},
doi = {10.1109/ASAP.2006.10},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/DimitrakopoulosMGN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DimitrakopoulosMGN06,
author = {Giorgos Dimitrakopoulos and
Christos Mavrokefalidis and
Costas Galanopoulos and
Dimitris Nikolos},
title = {Fast bit permutation unit for media enhanced microprocessors},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692519},
doi = {10.1109/ISCAS.2006.1692519},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DimitrakopoulosMGN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/DimitrakopoulosN05,
author = {Giorgos Dimitrakopoulos and
Dimitris Nikolos},
title = {High-Speed Parallel-Prefix {VLSI} Ling Adders},
journal = {{IEEE} Trans. Computers},
volume = {54},
number = {2},
pages = {225--231},
year = {2005},
url = {https://doi.org/10.1109/TC.2005.26},
doi = {10.1109/TC.2005.26},
timestamp = {Wed, 14 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/DimitrakopoulosN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/EfstathiouVDN05,
author = {Costas Efstathiou and
Haridimos T. Vergos and
Giorgos Dimitrakopoulos and
Dimitris Nikolos},
title = {Efficient Diminished-1 Modulo 2{\^{}}n+1 Multipliers},
journal = {{IEEE} Trans. Computers},
volume = {54},
number = {4},
pages = {491--496},
year = {2005},
url = {https://doi.org/10.1109/TC.2005.63},
doi = {10.1109/TC.2005.63},
timestamp = {Wed, 14 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/EfstathiouVDN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/DimitrakopoulosNVNE05,
author = {Giorgos Dimitrakopoulos and
Dimitris G. Nikolos and
Haridimos T. Vergos and
Dimitris Nikolos and
Costas Efstathiou},
title = {New architectures for modulo 2N - 1 adders},
booktitle = {12th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2005, Gammarth, Tunisia, December 11-14, 2005},
pages = {1--4},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ICECS.2005.4633502},
doi = {10.1109/ICECS.2005.4633502},
timestamp = {Tue, 25 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/DimitrakopoulosNVNE05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DimitrakopoulosN05,
author = {Giorgos Dimitrakopoulos and
Dimitris Nikolos},
editor = {Vassilis Paliouras and
Johan Vounckx and
Diederik Verkest},
title = {Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation, 15th International Workshop, {PATMOS} 2005, Leuven,
Belgium, September 21-23, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3728},
pages = {308--317},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11556930\_32},
doi = {10.1007/11556930\_32},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DimitrakopoulosN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/Dimitrakopoulos04,
author = {Giorgos Dimitrakopoulos and
Vassilis Paliouras},
title = {A novel architecture and a systematic graph-based optimization methodology
for modulo multiplication},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {51-I},
number = {2},
pages = {354--370},
year = {2004},
url = {https://doi.org/10.1109/TCSI.2003.820243},
doi = {10.1109/TCSI.2003.820243},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/Dimitrakopoulos04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DimitrakopoulosKKN04,
author = {Giorgos Dimitrakopoulos and
Pavlos Kolovos and
P. Kalogerakis and
Dimitris Nikolos},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Design of High-Speed Low-Power Parallel-Prefix {VLSI} Adders},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {248--257},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_27},
doi = {10.1007/978-3-540-30205-6\_27},
timestamp = {Fri, 15 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DimitrakopoulosKKN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/DimitrakopoulosVNE03,
author = {Giorgos Dimitrakopoulos and
Haridimos T. Vergos and
Dimitris Nikolos and
Costas Efstathiou},
title = {A Family of Parallel-Pre.x Modulo 2n - 1 Adders},
booktitle = {14th {IEEE} International Conference on Application-Specific Systems,
Architectures, and Processors {(ASAP} 2003), 24-26 June 2003, The
Hague, The Netherlands},
pages = {326--336},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ASAP.2003.1212856},
doi = {10.1109/ASAP.2003.1212856},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/DimitrakopoulosVNE03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/EfstathiouVDN03,
author = {Costas Efstathiou and
Haridimos T. Vergos and
Giorgos Dimitrakopoulos and
Dimitris Nikolos},
title = {Efficient modulo 2\({}^{\mbox{n}}\)+1 tree multipliers for diminished-1
operands},
booktitle = {Proceedings of the 2003 10th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2003, Sharjah, United Arab Emirates,
December 14-17, 2003},
pages = {200--203},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ICECS.2003.1302011},
doi = {10.1109/ICECS.2003.1302011},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/EfstathiouVDN03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DimitrakopoulosVNE03,
author = {Giorgos Dimitrakopoulos and
Haridimos T. Vergos and
Dimitris Nikolos and
Costas Efstathiou},
title = {A systematic methodology for designing area-time efficient parallel-prefix
modulo 2\({}^{\mbox{n}}\) - 1 adders},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {225--228},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206237},
doi = {10.1109/ISCAS.2003.1206237},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DimitrakopoulosVNE03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DimitrakopoulosKN03,
author = {Giorgos Dimitrakopoulos and
Xrysovalantis Kavousianos and
Dimitris Nikolos},
title = {Virtual-scan: a novel approach for software-based self-testing of
microprocessors},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {237--240},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206240},
doi = {10.1109/ISCAS.2003.1206240},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DimitrakopoulosKN03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/DimitrakopoulosNB02,
author = {Giorgos Dimitrakopoulos and
Dimitris Nikolos and
Dimitris Bakalis},
title = {Bit-Serial Test Pattern Generation by an Accumulator Behaving as a
Non-Linear Feedback Shift Register},
booktitle = {8th {IEEE} International On-Line Testing Workshop {(IOLTW} 2002),
8-10 July 2002, Isle of Bendor, France},
pages = {152--157},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/OLT.2002.1030199},
doi = {10.1109/OLT.2002.1030199},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/DimitrakopoulosNB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-03-24 00:12 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
