BibTeX records: Kangwook Jo

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@inproceedings{DBLP:conf/isscc/KimLHPPJNSLSCJAPOKKPLWKKCCPYLPHKCJCCC23,
  author       = {Bvunarvul Kim and
                  Seungpil Lee and
                  Beomseok Hah and
                  Kanawoo Park and
                  Yongsoon Park and
                  Kangwook Jo and
                  Yujong Noh and
                  Hyeon{-}Cheon Seol and
                  Hyunsoo Lee and
                  Jae{-}Hyeon Shin and
                  Seongjin Choi and
                  Youngdon Jung and
                  Sungho Ahn and
                  Yonghun Park and
                  Sujeong Oh and
                  Myungsu Kim and
                  Seonauk Kim and
                  Hyunwook Park and
                  Taeho Lee and
                  Haeun Won and
                  Minsung Kim and
                  Cheulhee Koo and
                  Yeonjoo Choi and
                  Suyoung Choi and
                  Sechun Park and
                  Dongkyu Youn and
                  Junyoun Lim and
                  Wonsun Park and
                  Hwang Hur and
                  Kichang Kwean and
                  Hongsok Choi and
                  Woopyo Jeong and
                  Sungyong Chung and
                  Jungdal Choi and
                  Seonyong Cha},
  title        = {A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write
                  Throughput on over 300 Layers {\textdollar}{\textbackslash}mathsf\{i\}{\textdollar}},
  booktitle    = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
                  San Francisco, CA, USA, February 19-23, 2023},
  pages        = {402--403},
  publisher    = {{IEEE}},
  year         = {2023},
  url          = {https://doi.org/10.1109/ISSCC42615.2023.10067666},
  doi          = {10.1109/ISSCC42615.2023.10067666},
  timestamp    = {Wed, 29 Mar 2023 15:53:39 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/KimLHPPJNSLSCJAPOKKPLWKKCCPYLPHKCJCCC23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/HuhCLNPOKCLKPKL20,
  author       = {Hwang Huh and
                  Wanik Cho and
                  Jinhaeng Lee and
                  Yujong Noh and
                  Yongsoon Park and
                  Sunghwa Ok and
                  Jongwoo Kim and
                  Kayoung Cho and
                  Hyunchul Lee and
                  Geonu Kim and
                  Kangwoo Park and
                  Kwanho Kim and
                  Heejoo Lee and
                  Sooyeol Chai and
                  Chankeun Kwon and
                  Hanna Cho and
                  Chanhui Jeong and
                  Yujin Yang and
                  Jayoon Goo and
                  Jangwon Park and
                  Juhyeong Lee and
                  Heonki Kirr and
                  Kangwook Jo and
                  Cheoljoong Park and
                  Hyeonsu Nam and
                  Hyunseok Song and
                  Sangkyu Lee and
                  Woopyo Jeong and
                  Kun{-}Ok Ahn and
                  Tae{-}Sung Jung},
  title        = {13.2 {A} 1Tb 4b/Cell 96-Stacked-WL 3D {NAND} Flash Memory with 30MB/s
                  Program Throughput Using Peripheral Circuit Under Memory Cell Array
                  Technique},
  booktitle    = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
                  2020, San Francisco, CA, USA, February 16-20, 2020},
  pages        = {220--221},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/ISSCC19947.2020.9063117},
  doi          = {10.1109/ISSCC19947.2020.9063117},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/HuhCLNPOKCLKPKL20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/JoY17,
  author       = {Kangwook Jo and
                  Hongil Yoon},
  title        = {Variation-Tolerant Sensing Circuit for Ultralow-Voltage Operation
                  of Spin-Torque Transfer Magnetic {RAM}},
  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume       = {64-II},
  number       = {5},
  pages        = {570--574},
  year         = {2017},
  url          = {https://doi.org/10.1109/TCSII.2016.2581038},
  doi          = {10.1109/TCSII.2016.2581038},
  timestamp    = {Wed, 27 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/JoY17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isocc/JoCY16,
  author       = {Kangwook Jo and
                  Kyungseon Cho and
                  Hongil Yoon},
  title        = {Variation-tolerant and low power look-up table {(LUT)} using spin-torque
                  transfer magnetic {RAM} for non-volatile field programmable gate array
                  {(FPGA)}},
  booktitle    = {International SoC Design Conference, {ISOCC} 2016, Jeju, South Korea,
                  October 23-26, 2016},
  pages        = {101--102},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISOCC.2016.7799753},
  doi          = {10.1109/ISOCC.2016.7799753},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isocc/JoCY16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isocc/ParkLPKRJJLYJCK12,
  author       = {Jaeseok Park and
                  Ingeol Lee and
                  Young{-}Seok Park and
                  Sung{-}Geun Kim and
                  Kyungho Ryu and
                  Dong{-}Hoon Jung and
                  Kangwook Jo and
                  Choong Keun Lee and
                  Hongil Yoon and
                  Seong{-}Ook Jung and
                  Woo{-}Young Choi and
                  Sungho Kang},
  title        = {Integration of dual channel timing formatter system for high speed
                  memory test equipment},
  booktitle    = {International SoC Design Conference, {ISOCC} 2012, Jeju Island, South
                  Korea, November 4-7, 2012},
  pages        = {185--187},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISOCC.2012.6407070},
  doi          = {10.1109/ISOCC.2012.6407070},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isocc/ParkLPKRJJLYJCK12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}