BibTeX records: Toshiyuki Oashi

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@article{DBLP:journals/jssc/NiiYTOIMYITOHSO08,
  author       = {Koji Nii and
                  Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Shigeki Ohbayashi and
                  Susumu Imaoka and
                  Hiroshi Makino and
                  Yoshinobu Yamagami and
                  Satoshi Ishikura and
                  Toshio Terano and
                  Toshiyuki Oashi and
                  Keiji Hashimoto and
                  Akio Sebe and
                  Gen Okazaki and
                  Katsuji Satomi and
                  Hironori Akamatsu and
                  Hirofumi Shinohara},
  title        = {A 45-nm Bulk {CMOS} Embedded {SRAM} With Improved Immunity Against
                  Process and Temperature Variations},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {43},
  number       = {1},
  pages        = {180--191},
  year         = {2008},
  url          = {https://doi.org/10.1109/JSSC.2007.907998},
  doi          = {10.1109/JSSC.2007.907998},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/NiiYTOIMYITOHSO08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/IshikuraKTYKSNY08,
  author       = {Satoshi Ishikura and
                  Marefusa Kurumada and
                  Toshio Terano and
                  Yoshinobu Yamagami and
                  Naoki Kotani and
                  Katsuji Satomi and
                  Koji Nii and
                  Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Shigeki Ohbayashi and
                  Toshiyuki Oashi and
                  Hiroshi Makino and
                  Hirofumi Shinohara and
                  Hironori Akamatsu},
  title        = {A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique
                  With Immunity From Simultaneous {R/W} Access Issues},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {43},
  number       = {4},
  pages        = {938--945},
  year         = {2008},
  url          = {https://doi.org/10.1109/JSSC.2008.917568},
  doi          = {10.1109/JSSC.2008.917568},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/IshikuraKTYKSNY08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/YabuuchiNTOIMYITOHSOSAS07,
  author       = {Makoto Yabuuchi and
                  Koji Nii and
                  Yasumasa Tsukamoto and
                  Shigeki Ohbayashi and
                  Susumu Imaoka and
                  Hiroshi Makino and
                  Yoshinobu Yamagami and
                  Satoshi Ishikura and
                  Toshio Terano and
                  Toshiyuki Oashi and
                  Keiji Hashimoto and
                  Akio Sebe and
                  Gen Okazaki and
                  Katsuji Satomi and
                  Hironori Akamatsu and
                  Hirofumi Shinohara},
  title        = {A 45nm Low-Standby-Power Embedded {SRAM} with Improved Immunity Against
                  Process and Temperature Variations},
  booktitle    = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2007, Digest of Technical Papers, San Francisco, CA, USA, February
                  11-15, 2007},
  pages        = {326--606},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/ISSCC.2007.373426},
  doi          = {10.1109/ISSCC.2007.373426},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/YabuuchiNTOIMYITOHSOSAS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ShimomuraSSOOYE97,
  author       = {Ken'ichi Shimomura and
                  Hiroki Shimano and
                  Narumi Sakashita and
                  Fumihiro Okuda and
                  Toshiyuki Oashi and
                  Yasuo Yamaguchi and
                  Takahisa Eimori and
                  Masahide Inuishi and
                  Kazutami Arimoto and
                  Shigeto Maegawa and
                  Yasuo Inoue and
                  Shinji Komori and
                  Kazuo Kyuma},
  title        = {A 1-V 46-ns 16-Mb {SOI-DRAM} with body control technique},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {32},
  number       = {11},
  pages        = {1712--1720},
  year         = {1997},
  url          = {https://doi.org/10.1109/4.641691},
  doi          = {10.1109/4.641691},
  timestamp    = {Thu, 07 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ShimomuraSSOOYE97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/SumaTHEOYIHMAFINY94,
  author       = {Katsuhiro Suma and
                  Takahiro Tsuruda and
                  Hideto Hidaka and
                  Takahisa Eimori and
                  Toshiyuki Oashi and
                  Yasuo Yamaguchi and
                  Toshiaki Iwamatsu and
                  Masakazu Hirose and
                  Fukashi Morishita and
                  Kazutarni Arimoto and
                  Kazuyasu Fujishima and
                  Yasuo Inoue and
                  Tadashi Nishimura and
                  Tsutomu Yoshihara},
  title        = {An {SOI-DRAM} with wide operating voltage range by {CMOS/SIMOX} technology},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {29},
  number       = {11},
  pages        = {1323--1329},
  year         = {1994},
  url          = {https://doi.org/10.1109/4.328631},
  doi          = {10.1109/4.328631},
  timestamp    = {Mon, 26 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/SumaTHEOYIHMAFINY94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}