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BibTeX records: Shenchen Ruan
@article{DBLP:journals/corr/RuanWW16, author = {Shenchen Ruan and Haixia Wang and Dongsheng Wang}, title = {{MAC:} a novel systematically multilevel cache replacement policy for {PCM} memory}, journal = {CoRR}, volume = {abs/1606.03248}, year = {2016}, url = {http://arxiv.org/abs/1606.03248}, eprinttype = {arXiv}, eprint = {1606.03248}, timestamp = {Wed, 31 Jan 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/corr/RuanWW16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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