Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Sachin S. Sapatnekar
@article{DBLP:journals/todaes/ChhabriaJKS24,
author = {Vidya A. Chhabria and
Wenjing Jiang and
Andrew B. Kahng and
Sachin S. Sapatnekar},
title = {A Machine Learning Approach to Improving Timing Consistency between
Global Route and Detailed Route},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {29},
number = {1},
pages = {18:1--18:25},
year = {2024},
url = {https://doi.org/10.1145/3626959},
doi = {10.1145/3626959},
timestamp = {Sat, 10 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ChhabriaJKS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/SudarshanMVSC24,
author = {Chetan Choppali Sudarshan and
Nikhil Matkar and
Sarma B. K. Vrudhula and
Sachin S. Sapatnekar and
Vidya A. Chhabria},
title = {{ECO-CHIP:} Estimation of Carbon Footprint of Chiplet-based Architectures
for Sustainable {VLSI}},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2024, Edinburgh, United Kingdom, March 2-6, 2024},
pages = {671--685},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/HPCA57654.2024.00058},
doi = {10.1109/HPCA57654.2024.00058},
timestamp = {Thu, 18 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/SudarshanMVSC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GuoSG24,
author = {Shiyu Guo and
Sachin S. Sapatnekar and
Jie Gu},
title = {2.5 {A} 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic
Augmented Reality with Inverse Rendering and Background Clustering
for Mobile Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {44--46},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454394},
doi = {10.1109/ISSCC49657.2024.10454394},
timestamp = {Tue, 19 Mar 2024 09:04:31 +0100},
biburl = {https://dblp.org/rec/conf/isscc/GuoSG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@misc{DBLP:data/10/CilasunMZILVTASKSKK24,
author = {H{\"{u}}srev Cilasun and
William Moy and
Ziqing Zeng and
Tahmida Islam and
Hao Lo and
Alex Vanasse and
Megan Tan and
Mohammad Anees and
Ramprasath S and
Abhimanyu Kumar and
Sachin S. Sapatnekar and
Chris H. Kim and
Ulya R. Karpuzcu},
title = {{COBI:} {A} Coupled Oscillator Based Ising Chip for Combinatorial
Optimization (Version 1.0)},
publisher = {Zenodo},
year = {2024},
month = jan,
howpublished = {\url{https://doi.org/10.5281/zenodo.10573584}},
note = {Accessed on YYYY-MM-DD.},
url = {https://doi.org/10.5281/zenodo.10573584},
doi = {10.5281/ZENODO.10573584},
timestamp = {Tue, 09 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/data/10/CilasunMZILVTASKSKK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2402-07781,
author = {Vidya A. Chhabria and
Wenjing Jiang and
Sachin S. Sapatnekar},
title = {IR-Aware {ECO} Timing Optimization Using Reinforcement Learning},
journal = {CoRR},
volume = {abs/2402.07781},
year = {2024},
url = {https://doi.org/10.48550/arXiv.2402.07781},
doi = {10.48550/ARXIV.2402.07781},
eprinttype = {arXiv},
eprint = {2402.07781},
timestamp = {Mon, 19 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2402-07781.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KarmokarSPMHS23,
author = {Nibedita Karmokar and
Arvind K. Sharma and
Jitesh Poojary and
Meghna Madhusudan and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {Constructive Placement and Routing for Common-Centroid Capacitor Arrays
in Binary-Weighted and Split DACs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {9},
pages = {2782--2795},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2023.3238880},
doi = {10.1109/TCAD.2023.3238880},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KarmokarSPMHS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KunalDMPSXBHHS23,
author = {Kishor Kunal and
Tonmoy Dhar and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Jiang Hu and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {GNN-Based Hierarchical Annotation for Analog Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {9},
pages = {2801--2814},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2023.3236269},
doi = {10.1109/TCAD.2023.3236269},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KunalDMPSXBHHS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MondalMKSZS23,
author = {Sudipta Mondal and
Susmita Dey Manasi and
Kishor Kunal and
Ramprasath S and
Ziqing Zeng and
Sachin S. Sapatnekar},
title = {A Unified Engine for Accelerating {GNN} Weighting/Aggregation Operations,
With Efficient Load Balancing and Graph-Specific Caching},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {12},
pages = {4844--4857},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3232467},
doi = {10.1109/TCAD.2022.3232467},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MondalMKSZS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChhabriaAPPJS23,
author = {Vidya A. Chhabria and
Vipul Ahuja and
Ashwath Prabhu and
Nikhil Patil and
Palkesh Jain and
Sachin S. Sapatnekar},
title = {Encoder-Decoder Networks for Analyzing Thermal and Power Delivery
Networks},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {28},
number = {1},
pages = {3:1--3:27},
year = {2023},
url = {https://doi.org/10.1145/3526115},
doi = {10.1145/3526115},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ChhabriaAPPJS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiLMSSHH23,
author = {Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Arvind K. Sharma and
Sachin S. Sapatnekar and
Ramesh Harjani and
Jiang Hu},
title = {Performance-driven Wire Sizing for Analog Integrated Circuits},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {28},
number = {2},
pages = {19:1--19:23},
year = {2023},
url = {https://doi.org/10.1145/3559542},
doi = {10.1145/3559542},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/LiLMSSHH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/GopalakrishnanMSPYHBS23,
author = {Ramprasath Srinivasa Gopalakrishnan and
Meghna Madhusudan and
Arvind K. Sharma and
Jitesh Poojary and
Soner Yaldiz and
Ramesh Harjani and
Steven M. Burns and
Sachin S. Sapatnekar},
title = {A Generalized Methodology for Well Island Generation and Well-tap
Insertion in Analog/Mixed-signal Layouts},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {28},
number = {5},
pages = {69:1--69:25},
year = {2023},
url = {https://doi.org/10.1145/3580477},
doi = {10.1145/3580477},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/GopalakrishnanMSPYHBS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ManasiBDSBKS23,
author = {Susmita Dey Manasi and
Suvadeep Banerjee and
Abhijit Davare and
Anton A. Sorokin and
Steven M. Burns and
Desmond A. Kirkpatrick and
Sachin S. Sapatnekar},
editor = {Atsushi Takahashi},
title = {Reusing {GEMM} Hardware for Efficient Execution of Depthwise Separable
Convolution on ASIC-Based {DNN} Accelerators},
booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2023, Tokyo, Japan, January 16-19, 2023},
pages = {475--482},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3566097.3567863},
doi = {10.1145/3566097.3567863},
timestamp = {Mon, 26 Jun 2023 20:46:40 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ManasiBDSBKS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KamineniSHSC23,
author = {Sumanth Kamineni and
Arvind K. Sharma and
Ramesh Harjani and
Sachin S. Sapatnekar and
Benton H. Calhoun},
title = {AuxcellGen: {A} Framework for Autonomous Generation of Analog and
Memory Unit Cells},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137270},
doi = {10.23919/DATE56975.2023.10137270},
timestamp = {Wed, 07 Jun 2023 22:08:03 +0200},
biburl = {https://dblp.org/rec/conf/date/KamineniSHSC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KarmokarHS23,
author = {Nibedita Karmokar and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor
Arrays},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137063},
doi = {10.23919/DATE56975.2023.10137063},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/KarmokarHS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ZengS23,
author = {Ziqing Zeng and
Sachin S. Sapatnekar},
title = {Energy-efficient Hardware Acceleration of Shallow Machine Learning
Applications},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137232},
doi = {10.23919/DATE56975.2023.10137232},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ZengS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/essderc/MadhusudanPSSKSH23,
author = {Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Ramprasath S and
Kishor Kunal and
Sachin S. Sapatnekar and
Ramesh Harjani},
title = {Understanding Distance-Dependent Variations for Analog Circuits in
a FinFET Technology},
booktitle = {53rd {IEEE} European Solid-State Device Research Conference, {ESSDERC}
2023, Lisbon, Portugal, September 11-14, 2023},
pages = {69--72},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ESSDERC59256.2023.10268572},
doi = {10.1109/ESSDERC59256.2023.10268572},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/essderc/MadhusudanPSSKSH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ShohelCES23,
author = {Mohammad Abdullah Al Shohel and
Vidya A. Chhabria and
Nestoras E. Evmorfopoulos and
Sachin S. Sapatnekar},
title = {Frequency-Domain Transient Electromigration Analysis Using Circuit
Theory},
booktitle = {{IEEE/ACM} International Conference on Computer Aided Design, {ICCAD}
2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCAD57390.2023.10323810},
doi = {10.1109/ICCAD57390.2023.10323810},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ShohelCES23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icrc/ReschCZCZWSK23,
author = {Salonik Resch and
H{\"{u}}srev Cilasun and
Masoud Zabihi and
Zamshed Iqbal Chowdhury and
Zhengyang Zhao and
Jian{-}Ping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {PimCity: {A} Compute in Memory Substrate featuring both Row and Column
Parallel Computing},
booktitle = {{IEEE} International Conference on Rebooting Computing, {ICRC} 2023,
San Diego, CA, USA, December 5-6, 2023},
pages = {1--10},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICRC60800.2023.10386151},
doi = {10.1109/ICRC60800.2023.10386151},
timestamp = {Wed, 24 Jan 2024 08:30:05 +0100},
biburl = {https://dblp.org/rec/conf/icrc/ReschCZCZWSK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ReschCCZZ0SK23,
author = {Salonik Resch and
M. H{\"{u}}srev Cilasun and
Zamshed I. Chowdhury and
Masoud Zabihi and
Zhengyang Zhao and
Jian{-}Ping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
editor = {Yan Solihin and
Mark A. Heinrich},
title = {On Endurance of Processing in (Nonvolatile) Memory},
booktitle = {Proceedings of the 50th Annual International Symposium on Computer
Architecture, {ISCA} 2023, Orlando, FL, USA, June 17-21, 2023},
pages = {79:1--79:13},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579371.3589114},
doi = {10.1145/3579371.3589114},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/ReschCCZZ0SK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/MondalSZKS23,
author = {Sudipta Mondal and
Ramprasath S and
Ziqing Zeng and
Kishor Kunal and
Sachin S. Sapatnekar},
title = {A Multicore {GNN} Training Accelerator},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2023, Vienna, Austria, August 7-8, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISLPED58423.2023.10244283},
doi = {10.1109/ISLPED58423.2023.10244283},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/MondalSZKS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/Sapatnekar23,
author = {Sachin S. Sapatnekar},
editor = {David G. Chinnery and
Iris Hui{-}Ru Jiang},
title = {The {ALIGN} Automated Analog Layout Engine: Progress, Learnings, and
Open Issues},
booktitle = {Proceedings of the 2023 International Symposium on Physical Design,
{ISPD} 2023, Virtual Event, USA, March 26-29, 2023},
pages = {101--102},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3569052.3578916},
doi = {10.1145/3569052.3578916},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispd/Sapatnekar23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/EvmorfopoulosSA23,
author = {Nestor E. Evmorfopoulos and
Mohammad Abdullah Al Shohel and
Olympia Axelou and
Pavlos Stoikos and
Vidya A. Chhabria and
Sachin S. Sapatnekar},
editor = {David G. Chinnery and
Iris Hui{-}Ru Jiang},
title = {Recent Progress in the Analysis of Electromigration and Stress Migration
in Large Multisegment Interconnects},
booktitle = {Proceedings of the 2023 International Symposium on Physical Design,
{ISPD} 2023, Virtual Event, USA, March 26-29, 2023},
pages = {115--123},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3569052.3578919},
doi = {10.1145/3569052.3578919},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispd/EvmorfopoulosSA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChhabriaS23,
author = {Vidya A. Chhabria and
Sachin S. Sapatnekar},
title = {Analysis of Pattern-dependent Rapid Thermal Annealing Effects on {SRAM}
Design},
booktitle = {24th International Symposium on Quality Electronic Design, {ISQED}
2023, San Francisco, CA, USA, April 5-7, 2023},
pages = {1--7},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISQED57927.2023.10129399},
doi = {10.1109/ISQED57927.2023.10129399},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/ChhabriaS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mlcad/LinLMSHH23,
author = {Yishuang Lin and
Yaguang Li and
Meghna Madhusudan and
Sachin S. Sapatnekar and
Ramesh Harjani and
Jiang Hu},
title = {{MMM:} Machine Learning-Based Macro-Modeling for Linear Analog ICs
and ADC/DACs},
booktitle = {5th {ACM/IEEE} Workshop on Machine Learning for CAD, {MLCAD} 2023,
Snowbird, UT, USA, September 10-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MLCAD58807.2023.10299829},
doi = {10.1109/MLCAD58807.2023.10299829},
timestamp = {Wed, 15 Nov 2023 09:43:46 +0100},
biburl = {https://dblp.org/rec/conf/mlcad/LinLMSHH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2305-06917,
author = {Vidya A. Chhabria and
Wenjing Jiang and
Andrew B. Kahng and
Sachin S. Sapatnekar},
title = {A Machine Learning Approach to Improving Timing Consistency between
Global Route and Detailed Route},
journal = {CoRR},
volume = {abs/2305.06917},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2305.06917},
doi = {10.48550/ARXIV.2305.06917},
eprinttype = {arXiv},
eprint = {2305.06917},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2305-06917.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2306-09434,
author = {Vidya A. Chhabria and
Chetan Choppali Sudarshan and
Sarma B. K. Vrudhula and
Sachin S. Sapatnekar},
title = {Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous
Systems},
journal = {CoRR},
volume = {abs/2306.09434},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2306.09434},
doi = {10.48550/ARXIV.2306.09434},
eprinttype = {arXiv},
eprint = {2306.09434},
timestamp = {Tue, 16 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2306-09434.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2306-16767,
author = {Hadi Esmaeilzadeh and
Soroush Ghodrati and
Andrew B. Kahng and
Sean Kinzer and
Susmita Dey Manasi and
Sachin S. Sapatnekar and
Zhiang Wang},
title = {Performance Analysis of {DNN} Inference/Training with Convolution
and non-Convolution Operations},
journal = {CoRR},
volume = {abs/2306.16767},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2306.16767},
doi = {10.48550/ARXIV.2306.16767},
eprinttype = {arXiv},
eprint = {2306.16767},
timestamp = {Mon, 03 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2306-16767.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2308-12120,
author = {Hadi Esmaeilzadeh and
Soroush Ghodrati and
Andrew B. Kahng and
Joon Kyung Kim and
Sean Kinzer and
Sayak Kundu and
Rohan Mahapatra and
Susmita Dey Manasi and
Sachin S. Sapatnekar and
Zhiang Wang and
Ziqing Zeng},
title = {An Open-Source ML-Based Full-Stack Optimization Framework for Machine
Learning Accelerators},
journal = {CoRR},
volume = {abs/2308.12120},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2308.12120},
doi = {10.48550/ARXIV.2308.12120},
eprinttype = {arXiv},
eprint = {2308.12120},
timestamp = {Wed, 30 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2308-12120.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2309-11017,
author = {M. H{\"{u}}srev Cilasun and
Ziqing Zeng and
Ramprasath S and
Abhimanyu Kumar and
Hao Lo and
William Cho and
Chris H. Kim and
Ulya R. Karpuzcu and
Sachin S. Sapatnekar},
title = {3SAT on an All-to-All-Connected {CMOS} Ising Solver Chip},
journal = {CoRR},
volume = {abs/2309.11017},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2309.11017},
doi = {10.48550/ARXIV.2309.11017},
eprinttype = {arXiv},
eprint = {2309.11017},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2309-11017.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2312-14264,
author = {Yang Lv and
Brandon R. Zink and
Robert P. Bloom and
M. H{\"{u}}srev Cilasun and
Pravin Khanal and
Salonik Resch and
Zamshed I. Chowdhury and
Ali Habiboglu and
Weigang Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuczu and
Jianping Wang},
title = {Experimental demonstration of magnetic tunnel junction-based computational
random-access memory},
journal = {CoRR},
volume = {abs/2312.14264},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2312.14264},
doi = {10.48550/ARXIV.2312.14264},
eprinttype = {arXiv},
eprint = {2312.14264},
timestamp = {Wed, 17 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2312-14264.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChhabriaS22,
author = {Vidya A. Chhabria and
Sachin S. Sapatnekar},
title = {OpeNPDN: {A} Neural-Network-Based Framework for Power Delivery Network
Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {10},
pages = {3515--3528},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3132554},
doi = {10.1109/TCAD.2021.3132554},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChhabriaS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/ReschKCZZCWSK22,
author = {Salonik Resch and
S. Karen Khatamifard and
Zamshed I. Chowdhury and
Masoud Zabihi and
Zhengyang Zhao and
M. H{\"{u}}srev Cilasun and
Jianping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {Energy-efficient and Reliable Inference in Nonvolatile Memory under
Extreme Operating Conditions},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {21},
number = {5},
pages = {57:1--57:36},
year = {2022},
url = {https://doi.org/10.1145/3520130},
doi = {10.1145/3520130},
timestamp = {Wed, 21 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tecs/ReschKCZZCWSK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tetc/ChowdhuryKRCZZR22,
author = {Zamshed I. Chowdhury and
S. Karen Khatamifard and
Salonik Resch and
M. H{\"{u}}srev Cilasun and
Zhengyang Zhao and
Masoud Zabihi and
Meisam Razaviyayn and
Jian{-}Ping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational
{RAM}},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {10},
number = {4},
pages = {2055--2071},
year = {2022},
url = {https://doi.org/10.1109/TETC.2022.3153613},
doi = {10.1109/TETC.2022.3153613},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tetc/ChowdhuryKRCZZR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KarmokarMSHLS22,
author = {Nibedita Karmokar and
Meghna Madhusudan and
Arvind K. Sharma and
Ramesh Harjani and
Mark Po{-}Hung Lin and
Sachin S. Sapatnekar},
title = {Common-Centroid Layout for Active and Passive Devices: {A} Review
and the Road Ahead},
booktitle = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2022, Taipei, Taiwan, January 17-20, 2022},
pages = {114--121},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASP-DAC52403.2022.9712576},
doi = {10.1109/ASP-DAC52403.2022.9712576},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KarmokarMSHLS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MondalMKSS22,
author = {Sudipta Mondal and
Susmita Dey Manasi and
Kishor Kunal and
Ramprasath S and
Sachin S. Sapatnekar},
editor = {Rob Oshana},
title = {{GNNIE:} {GNN} inference engine with load-balancing and graph-specific
caching},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {565--570},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530503},
doi = {10.1145/3489517.3530503},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/MondalMKSS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DharSPYBHS22,
author = {Tonmoy Dhar and
Ramprasath S and
Jitesh Poojary and
Soner Yaldiz and
Steven M. Burns and
Ramesh Harjani and
Sachin S. Sapatnekar},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {148--153},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774621},
doi = {10.23919/DATE54114.2022.9774621},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/DharSPYBHS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LinLFMSHH22,
author = {Yishuang Lin and
Yaguang Li and
Donghao Fang and
Meghna Madhusudan and
Sachin S. Sapatnekar and
Ramesh Harjani and
Jiang Hu},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {Are Analytical Techniques Worthwhile for Analog {IC} Placement?},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {154--159},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774498},
doi = {10.23919/DATE54114.2022.9774498},
timestamp = {Wed, 25 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LinLFMSHH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KarmokarSPMHS22,
author = {Nibedita Karmokar and
Arvind K. Sharma and
Jitesh Poojary and
Meghna Madhusudan and
Ramesh Harjani and
Sachin S. Sapatnekar},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {Constructive Common-Centroid Placement and Routing for Binary-Weighted
Capacitor Arrays},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {166--171},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774640},
doi = {10.23919/DATE54114.2022.9774640},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/KarmokarSPMHS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/AxelouE0SS22,
author = {Olympia Axelou and
Nestor E. Evmorfopoulos and
George Floros and
George I. Stamoulis and
Sachin S. Sapatnekar},
editor = {Tulika Mitra and
Evangeline F. Y. Young and
Jinjun Xiong},
title = {A Novel Semi-Analytical Approach for Fast Electromigration Stress
Analysis in Multi-Segment Interconnects},
booktitle = {Proceedings of the 41st {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2022, San Diego, California, USA, 30 October 2022
- 3 November 2022},
pages = {27:1--27:7},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3508352.3549476},
doi = {10.1145/3508352.3549476},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/AxelouE0SS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/Sapatnekar22,
author = {Sachin S. Sapatnekar},
title = {{EDAML} 2022 Invited Speaker 7: Analog and Digital Circuit and Layout
Optimization using Machine Learning},
booktitle = {{IEEE} International Parallel and Distributed Processing Symposium,
{IPDPS} Workshops 2022, Lyon, France, May 30 - June 3, 2022},
pages = {1188},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IPDPSW55747.2022.00200},
doi = {10.1109/IPDPSW55747.2022.00200},
timestamp = {Mon, 08 Aug 2022 16:44:20 +0200},
biburl = {https://dblp.org/rec/conf/ipps/Sapatnekar22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/SMSPYHBS22,
author = {Ramprasath S and
Meghna Madhusudan and
Arvind K. Sharma and
Jitesh Poojary and
Soner Yaldiz and
Ramesh Harjani and
Steven M. Burns and
Sachin S. Sapatnekar},
editor = {Laleh Behjat and
Stephen Yang},
title = {Analog/Mixed-Signal Layout Optimization using Optimal Well Taps},
booktitle = {{ISPD} 2022: International Symposium on Physical Design, Virtual Event,
Canada, March 27 - 30, 2022},
pages = {159--166},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3505170.3506728},
doi = {10.1145/3505170.3506728},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispd/SMSPYHBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mlcad/ChhabriaJKS22,
author = {Vidya A. Chhabria and
Wenjing Jiang and
Andrew B. Kahng and
Sachin S. Sapatnekar},
title = {From Global Route to Detailed Route: {ML} for Fast and Accurate Wire
Parasitics and Timing Prediction},
booktitle = {2022 {ACM/IEEE} Workshop on Machine Learning for CAD, {MLCAD} 2022,
Virtual Event, China, September 12-13, 2022},
pages = {7--14},
publisher = {{ACM} / {IEEE}},
year = {2022},
url = {https://doi.org/10.1145/3551901.3556475},
doi = {10.1145/3551901.3556475},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mlcad/ChhabriaJKS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mlcad/EsmaeilzadehGKK22,
author = {Hadi Esmaeilzadeh and
Soroush Ghodrati and
Andrew B. Kahng and
Joon Kyung Kim and
Sean Kinzer and
Sayak Kundu and
Rohan Mahapatra and
Susmita Dey Manasi and
Sachin S. Sapatnekar and
Zhiang Wang and
Ziqing Zeng},
title = {Physically Accurate Learning-based Performance Prediction of Hardware-accelerated
{ML} Algorithms},
booktitle = {2022 {ACM/IEEE} Workshop on Machine Learning for CAD, {MLCAD} 2022,
Virtual Event, China, September 12-13, 2022},
pages = {119--126},
publisher = {{ACM} / {IEEE}},
year = {2022},
url = {https://doi.org/10.1145/3551901.3556489},
doi = {10.1145/3551901.3556489},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mlcad/EsmaeilzadehGKK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2207-13261,
author = {M. H{\"{u}}srev Cilasun and
Salonik Resch and
Zamshed I. Chowdhury and
Masoud Zabihi and
Yang Lv and
Brandon Zink and
Jianping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {Error Detection and Correction for Processing in Memory (PiM)},
journal = {CoRR},
volume = {abs/2207.13261},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2207.13261},
doi = {10.48550/ARXIV.2207.13261},
eprinttype = {arXiv},
eprint = {2207.13261},
timestamp = {Mon, 01 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2207-13261.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/DharKLMPSXBHHKM21,
author = {Tonmoy Dhar and
Kishor Kunal and
Yaguang Li and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Desmond A. Kirkpatrick and
Parijat Mukherjee and
Soner Yaldiz and
Sachin S. Sapatnekar},
title = {{ALIGN:} {A} System for Automating Analog Layout},
journal = {{IEEE} Des. Test},
volume = {38},
number = {2},
pages = {8--18},
year = {2021},
url = {https://doi.org/10.1109/MDAT.2020.3042177},
doi = {10.1109/MDAT.2020.3042177},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/DharKLMPSXBHHKM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/EversonSK21,
author = {Luke R. Everson and
Sachin S. Sapatnekar and
Chris H. Kim},
title = {A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront
Expansion and 2-D Gradient Control},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {7},
pages = {2281--2290},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2020.3048726},
doi = {10.1109/JSSC.2020.3048726},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/EversonSK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/CilasunRCOZZPPW21,
author = {M. H{\"{u}}srev Cilasun and
Salonik Resch and
Zamshed I. Chowdhury and
Erin Olson and
Masoud Zabihi and
Zhengyang Zhao and
Thomas Peterson and
Keshab K. Parhi and
Jianping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {Spiking Neural Networks in Spintronic Computational {RAM}},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {18},
number = {4},
pages = {59:1--59:21},
year = {2021},
url = {https://doi.org/10.1145/3475963},
doi = {10.1145/3475963},
timestamp = {Tue, 16 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/CilasunRCOZZPPW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SnigdhaMHS21,
author = {Farhana Sharmin Snigdha and
Susmita Dey Manasi and
Jiang Hu and
Sachin S. Sapatnekar},
title = {SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using
Optimized Thresholds},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {7},
pages = {1423--1436},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3016281},
doi = {10.1109/TCAD.2020.3016281},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SnigdhaMHS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DharPLKMSMHHS21,
author = {Tonmoy Dhar and
Jitesh Poojary and
Yaguang Li and
Kishor Kunal and
Meghna Madhusudan and
Arvind K. Sharma and
Susmita Dey Manasi and
Jiang Hu and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {Fast and Efficient Constraint Evaluation of Analog Layout Using Machine
Learning Models},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {158--163},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431547},
doi = {10.1145/3394885.3431547},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/DharPLKMSMHHS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ManasiS21,
author = {Susmita Dey Manasi and
Sachin S. Sapatnekar},
title = {DeepOpt: Optimized Scheduling of {CNN} Workloads for ASIC-based Systolic
Deep Learning Accelerators},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {235--241},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431539},
doi = {10.1145/3394885.3431539},
timestamp = {Tue, 09 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ManasiS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChhabriaAPPJS21,
author = {Vidya A. Chhabria and
Vipul Ahuja and
Ashwath Prabhu and
Nikhil Patil and
Palkesh Jain and
Sachin S. Sapatnekar},
title = {Thermal and {IR} Drop Analysis Using Convolutional Encoder-Decoder
Networks},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {690--696},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431583},
doi = {10.1145/3394885.3431583},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ChhabriaAPPJS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ShohelCS21,
author = {Mohammad Abdullah Al Shohel and
Vidya A. Chhabria and
Sachin S. Sapatnekar},
title = {A New, Computationally Efficient "Blech Criterion" for Immortality
in General Interconnects},
booktitle = {58th {ACM/IEEE} Design Automation Conference, {DAC} 2021, San Francisco,
CA, USA, December 5-9, 2021},
pages = {913--918},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DAC18074.2021.9586127},
doi = {10.1109/DAC18074.2021.9586127},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/ShohelCS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SharmaMBMYHS21,
author = {Arvind K. Sharma and
Meghna Madhusudan and
Steven M. Burns and
Parijat Mukherjee and
Soner Yaldiz and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {Common-Centroid Layouts for Analog Circuits: Advantages and Limitations},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1224--1229},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474244},
doi = {10.23919/DATE51398.2021.9474244},
timestamp = {Wed, 21 Jul 2021 10:04:34 +0200},
biburl = {https://dblp.org/rec/conf/date/SharmaMBMYHS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MadhusudanSLHSH21,
author = {Meghna Madhusudan and
Arvind K. Sharma and
Yaguang Li and
Jiang Hu and
Sachin S. Sapatnekar and
Ramesh Hajiani},
title = {Analog Layout Generation using Optimized Primitives},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1234--1239},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474010},
doi = {10.23919/DATE51398.2021.9474010},
timestamp = {Wed, 21 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MadhusudanSLHSH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChhabriaZRKKS21,
author = {Vidya A. Chhabria and
Yanqing Zhang and
Haoxing Ren and
Ben Keller and
Brucek Khailany and
Sachin S. Sapatnekar},
title = {{MAVIREC:} ML-Aided Vectored IR-Drop Estimation and Classification},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1825--1828},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9473914},
doi = {10.23919/DATE51398.2021.9473914},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ChhabriaZRKKS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChowdhuryRCZZSW21,
author = {Zamshed I. Chowdhury and
Salonik Resch and
M. H{\"{u}}srev Cilasun and
Zhengyang Zhao and
Masoud Zabihi and
Sachin S. Sapatnekar and
Jianping Wang and
Ulya R. Karpuzcu},
editor = {Yiran Chen and
Victor V. Zhirnov and
Avesta Sasan and
Ioannis Savidis},
title = {CAMeleon: Reconfigurable {B(T)CAM} in Computational {RAM}},
booktitle = {{GLSVLSI} '21: Great Lakes Symposium on {VLSI} 2021, Virtual Event,
USA, June 22-25, 2021},
pages = {57--63},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3453688.3461507},
doi = {10.1145/3453688.3461507},
timestamp = {Mon, 04 Jul 2022 14:19:34 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ChowdhuryRCZZSW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChhabriaKZS21,
author = {Vidya A. Chhabria and
Kishor Kunal and
Masoud Zabihi and
Sachin S. Sapatnekar},
title = {BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based
Methodology},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--8},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643566},
doi = {10.1109/ICCAD51958.2021.9643566},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ChhabriaKZS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/EsmaeilzadehG0G21,
author = {Hadi Esmaeilzadeh and
Soroush Ghodrati and
Jie Gu and
Shiyu Guo and
Andrew B. Kahng and
Joon Kyung Kim and
Sean Kinzer and
Rohan Mahapatra and
Susmita Dey Manasi and
Edwin Mascarenhas and
Sachin S. Sapatnekar and
Ravi Varadarajan and
Zhiang Wang and
Hanyang Xu and
Brahmendra Reddy Yatham and
Ziqing Zeng},
title = {VeriGOOD-ML: An Open-Source Flow for Automated {ML} Hardware Synthesis},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--7},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643449},
doi = {10.1109/ICCAD51958.2021.9643449},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/EsmaeilzadehG0G21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiuSMHSZRLHSSHL21,
author = {Juzheng Liu and
Shiyu Su and
Meghna Madhusudan and
Mohsen Hassanpourghadi and
Samuel Saunders and
Qiaochu Zhang and
Rezwan A. Rasul and
Yaguang Li and
Jiang Hu and
Arvind Kumar Sharma and
Sachin S. Sapatnekar and
Ramesh Harjani and
Anthony Levi and
Sandeep Gupta and
Mike Shuo{-}Wei Chen},
title = {From Specification to Silicon: Towards Analog/Mixed-Signal Design
Automation using Surrogate {NN} Models with Transfer Learning},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--9},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643445},
doi = {10.1109/ICCAD51958.2021.9643445},
timestamp = {Thu, 21 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LiuSMHSZRLHSSHL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SharmaMBYMHS21,
author = {Arvind K. Sharma and
Meghna Madhusudan and
Steven M. Burns and
Soner Yaldiz and
Parijat Mukherjee and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {Performance-Aware Common-Centroid Placement and Routing of Transistor
Arrays in Analog Circuits},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--9},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643532},
doi = {10.1109/ICCAD51958.2021.9643532},
timestamp = {Tue, 28 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SharmaMBYMHS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ShohelCES21,
author = {Mohammad Abdullah Al Shohel and
Vidya A. Chhabria and
Nestor E. Evmorfopoulos and
Sachin S. Sapatnekar},
title = {Analytical Modeling of Transient Electromigration Stress based on
Boundary Reflections},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--8},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643570},
doi = {10.1109/ICCAD51958.2021.9643570},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ShohelCES21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irps/DharPHS21,
author = {Tonmoy Dhar and
Jitesh Poojary and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {Aging of Current DACs and its Impact in Equalizer Circuits},
booktitle = {{IEEE} International Reliability Physics Symposium, {IRPS} 2021, Monterey,
CA, USA, March 21-25, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/IRPS46558.2021.9405160},
doi = {10.1109/IRPS46558.2021.9405160},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/irps/DharPHS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/DharKLLMPSBHHMY21,
author = {Tonmoy Dhar and
Kishor Kunal and
Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Parijat Mukherjee and
Soner Yaldiz and
Sachin S. Sapatnekar},
editor = {Jens Lienig and
Laleh Behjat and
Stephen Yang},
title = {Machine Learning Techniques in Analog Layout Automation},
booktitle = {{ISPD} '21: International Symposium on Physical Design, Virtual Event,
USA, March 22-24, 2021},
pages = {71--72},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3439706.3446896},
doi = {10.1145/3439706.3446896},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/DharKLLMPSBHHMY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mlcad/LiLMSSHH21,
author = {Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Arvind K. Sharma and
Sachin S. Sapatnekar and
Ramesh Harjani and
Jiang Hu},
title = {A Circuit Attention Network-Based Actor-Critic Learning Approach to
Robust Analog Transistor Sizing},
booktitle = {3rd {ACM/IEEE} Workshop on Machine Learning for CAD, {MLCAD} 2021,
Raleigh, NC, USA, August 30 - Sept. 3, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MLCAD52597.2021.9531156},
doi = {10.1109/MLCAD52597.2021.9531156},
timestamp = {Fri, 17 Sep 2021 14:46:40 +0200},
biburl = {https://dblp.org/rec/conf/mlcad/LiLMSSHH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/seed/CilasunRCZZPWSK21,
author = {M. H{\"{u}}srev Cilasun and
Salonik Resch and
Zamshed I. Chowdhury and
Masoud Zabihi and
Zhengyang Zhao and
Thomas Peterson and
Jian{-}Ping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {Seeds of {SEED:} {H-CRAM:} In-memory Homomorphic Search Accelerator
using Spintronic Computational {RAM}},
booktitle = {2021 International Symposium on Secure and Private Execution Environment
Design (SEED), Washington, DC, USA, September 20-21, 2021},
pages = {70--75},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SEED51797.2021.00018},
doi = {10.1109/SEED51797.2021.00018},
timestamp = {Wed, 21 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/seed/CilasunRCZZPWSK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2105-08784,
author = {Mohammad Abdullah Al Shohel and
Vidya A. Chhabria and
Sachin S. Sapatnekar},
title = {A New, Computationally Efficient "Blech Criterion" for Immortality
in General Interconnects},
journal = {CoRR},
volume = {abs/2105.08784},
year = {2021},
url = {https://arxiv.org/abs/2105.08784},
eprinttype = {arXiv},
eprint = {2105.08784},
timestamp = {Mon, 31 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2105-08784.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2105-10554,
author = {Sudipta Mondal and
Susmita Dey Manasi and
Kishor Kunal and
Sachin S. Sapatnekar},
title = {{GNNIE:} {GNN} Inference Engine with Load-balancing and Graph-Specific
Caching},
journal = {CoRR},
volume = {abs/2105.10554},
year = {2021},
url = {https://arxiv.org/abs/2105.10554},
eprinttype = {arXiv},
eprint = {2105.10554},
timestamp = {Mon, 31 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2105-10554.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2106-08402,
author = {Masoud Zabihi and
Salonik Resch and
M. H{\"{u}}srev Cilasun and
Zamshed I. Chowdhury and
Zhengyang Zhao and
Ulya R. Karpuzcu and
Jianping Wang and
Sachin S. Sapatnekar},
title = {Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing
Accelerator},
journal = {CoRR},
volume = {abs/2106.08402},
year = {2021},
url = {https://arxiv.org/abs/2106.08402},
eprinttype = {arXiv},
eprint = {2106.08402},
timestamp = {Mon, 15 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2106-08402.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2110-14184,
author = {Vidya A. Chhabria and
Sachin S. Sapatnekar},
title = {OpeNPDN: {A} Neural-network-based Framework for Power Delivery Network
Synthesis},
journal = {CoRR},
volume = {abs/2110.14184},
year = {2021},
url = {https://arxiv.org/abs/2110.14184},
eprinttype = {arXiv},
eprint = {2110.14184},
timestamp = {Fri, 29 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2110-14184.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2110-14197,
author = {Vidya A. Chhabria and
Vipul Ahuja and
Ashwath Prabhu and
Nikhil Patil and
Palkesh Jain and
Sachin S. Sapatnekar},
title = {Encoder-Decoder Networks for Analyzing Thermal and Power Delivery
Networks},
journal = {CoRR},
volume = {abs/2110.14197},
year = {2021},
url = {https://arxiv.org/abs/2110.14197},
eprinttype = {arXiv},
eprint = {2110.14197},
timestamp = {Fri, 29 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2110-14197.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2112-08943,
author = {Salonik Resch and
Zamshed I. Chowdhury and
M. H{\"{u}}srev Cilasun and
Masoud Zabihi and
Zhengyang Zhao and
Jian{-}Ping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {Towards Homomorphic Inference Beyond the Edge},
journal = {CoRR},
volume = {abs/2112.08943},
year = {2021},
url = {https://arxiv.org/abs/2112.08943},
eprinttype = {arXiv},
eprint = {2112.08943},
timestamp = {Wed, 21 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2112-08943.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2112-13451,
author = {Mohammad Abdullah Al Shohel and
Vidya A. Chhabria and
Sachin S. Sapatnekar},
title = {A Linear-Time Algorithm for Steady-State Analysis of Electromigration
in General Interconnects},
journal = {CoRR},
volume = {abs/2112.13451},
year = {2021},
url = {https://arxiv.org/abs/2112.13451},
eprinttype = {arXiv},
eprint = {2112.13451},
timestamp = {Tue, 04 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2112-13451.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/ReschKCZZ0SK20,
author = {Salonik Resch and
S. Karen Khatamifard and
Zamshed Iqbal Chowdhury and
Masoud Zabihi and
Zhengyang Zhao and
Jianping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {{PIMBALL:} Binary Neural Networks in Spintronic Memory},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {16},
number = {4},
pages = {41:1--41:26},
year = {2020},
url = {https://doi.org/10.1145/3357250},
doi = {10.1145/3357250},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/ReschKCZZ0SK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/FanLS20,
author = {Qianqian Fan and
David J. Lilja and
Sachin S. Sapatnekar},
title = {Adaptive-Length Coding of Image Data for Low-Cost Approximate Storage},
journal = {{IEEE} Trans. Computers},
volume = {69},
number = {2},
pages = {239--252},
year = {2020},
url = {https://doi.org/10.1109/TC.2019.2946795},
doi = {10.1109/TC.2019.2946795},
timestamp = {Thu, 06 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/FanLS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ManasiSS20,
author = {Susmita Dey Manasi and
Farhana Sharmin Snigdha and
Sachin S. Sapatnekar},
title = {NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning
of {CNN} Computations on Cloud-Connected Mobile Clients},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1844--1857},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2995135},
doi = {10.1109/TVLSI.2020.2995135},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ManasiSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChhabriaKKMSX20,
author = {Vidya A. Chhabria and
Andrew B. Kahng and
Minsoo Kim and
Uday Mallappa and
Sachin S. Sapatnekar and
Bangqi Xu},
title = {Template-based {PDN} Synthesis in Floorplan and Placement Using Classifier
and {CNN} Techniques},
booktitle = {25th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2020, Beijing, China, January 13-16, 2020},
pages = {44--49},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ASP-DAC47756.2020.9045303},
doi = {10.1109/ASP-DAC47756.2020.9045303},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChhabriaKKMSX20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/CilasunRCOZZPWS20,
author = {M. H{\"{u}}srev Cilasun and
Salonik Resch and
Zamshed Iqbal Chowdhury and
Erin Olson and
Masoud Zabihi and
Zhengyang Zhao and
Thomas Peterson and
Jianping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {{CRAFFT:} High Resolution {FFT} Accelerator In Spintronic Computational
{RAM}},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218673},
doi = {10.1109/DAC18072.2020.9218673},
timestamp = {Mon, 15 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/CilasunRCOZZPWS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KunalDMPSXBHHS20,
author = {Kishor Kunal and
Tonmoy Dhar and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Jiang Hu and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {{GANA:} Graph Convolutional Network Based Automated Netlist Annotation
for Analog Circuits},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {55--60},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116329},
doi = {10.23919/DATE48585.2020.9116329},
timestamp = {Wed, 19 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/KunalDMPSXBHHS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/DharKLLMPSBHHMY20,
author = {Tonmoy Dhar and
Kishor Kunal and
Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Parijat Mukherjee and
Soner Yaldiz and
Sachin S. Sapatnekar},
title = {The {ALIGN} Open-Source Analog Layout Generator: v1.0 and Beyond (Invited
talk)},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {54:1--54:2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415784},
doi = {10.1145/3400302.3415784},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/DharKLLMPSBHHMY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KunalPDMHS20,
author = {Kishor Kunal and
Jitesh Poojary and
Tonmoy Dhar and
Meghna Madhusudan and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {A general approach for identifying hierarchical symmetry constraints
for analog circuit layout},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {120:1--120:8},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415685},
doi = {10.1145/3400302.3415685},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/KunalPDMHS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiLMSXSHH20,
author = {Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Arvind K. Sharma and
Wenbin Xu and
Sachin S. Sapatnekar and
Ramesh Harjani and
Jiang Hu},
title = {A Customized Graph Neural Network Model for Guiding Analog {IC} Placement},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {135:1--135:9},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415624},
doi = {10.1145/3400302.3415624},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LiLMSXSHH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/KunalDLMPSXBHHM20,
author = {Kishor Kunal and
Tonmoy Dhar and
Yaguang Li and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Parijat Mukherjee and
Sachin S. Sapatnekar},
editor = {William Swartz and
Jens Lienig},
title = {Learning from Experience: Applying {ML} to Analog Circuit Design},
booktitle = {{ISPD} 2020: International Symposium on Physical Design, Taipei, Taiwan,
March 29 - April 1, 2020, delayed to September 20-23, 2020},
pages = {55},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3372780.3378172},
doi = {10.1145/3372780.3378172},
timestamp = {Wed, 19 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispd/KunalDLMPSXBHHM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LiS20,
author = {Tengtao Li and
Sachin S. Sapatnekar},
title = {Stress-Induced Performance Shifts in Flexible System-in-Foils Using
Ultra-Thin Chips},
booktitle = {21st International Symposium on Quality Electronic Design, {ISQED}
2020, Santa Clara, CA, USA, March 25-26, 2020},
pages = {237--242},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISQED48828.2020.9136992},
doi = {10.1109/ISQED48828.2020.9136992},
timestamp = {Wed, 22 Jul 2020 15:06:46 +0200},
biburl = {https://dblp.org/rec/conf/isqed/LiS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiLMSXSHH20,
author = {Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Arvind K. Sharma and
Wenbin Xu and
Sachin S. Sapatnekar and
Ramesh Harjani and
Jiang Hu},
title = {Exploring a Machine Learning Approach to Performance Driven Analog
{IC} Placement},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2020,
Limassol, Cyprus, July 6-8, 2020},
pages = {24--29},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISVLSI49217.2020.00015},
doi = {10.1109/ISVLSI49217.2020.00015},
timestamp = {Wed, 12 Aug 2020 14:38:21 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/LiLMSXSHH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/ReschKCZZCWSK20,
author = {Salonik Resch and
S. Karen Khatamifard and
Zamshed I. Chowdhury and
Masoud Zabihi and
Zhengyang Zhao and
M. H{\"{u}}srev Cilasun and
Jianping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {{MOUSE:} Inference In Non-volatile Memory for Energy Harvesting Applications},
booktitle = {53rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
{MICRO} 2020, Athens, Greece, October 17-21, 2020},
pages = {400--414},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MICRO50266.2020.00042},
doi = {10.1109/MICRO50266.2020.00042},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/ReschKCZZCWSK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2006-03007,
author = {M. H{\"{u}}srev Cilasun and
Salonik Resch and
Zamshed I. Chowdhury and
Erin Olson and
Masoud Zabihi and
Zhengyang Zhao and
Thomas Peterson and
Keshab K. Parhi and
Jianping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {An Inference and Learning Engine for Spiking Neural Networks in Computational
{RAM} {(CRAM)}},
journal = {CoRR},
volume = {abs/2006.03007},
year = {2020},
url = {https://arxiv.org/abs/2006.03007},
eprinttype = {arXiv},
eprint = {2006.03007},
timestamp = {Mon, 15 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2006-03007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2008-10682,
author = {Tonmoy Dhar and
Kishor Kunal and
Yaguang Li and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Desmond A. Kirkpatrick and
Parijat Mukherjee and
Sachin S. Sapatnekar and
Soner Yaldiz},
title = {{ALIGN:} {A} System for Automating Analog Layout},
journal = {CoRR},
volume = {abs/2008.10682},
year = {2020},
url = {https://arxiv.org/abs/2008.10682},
eprinttype = {arXiv},
eprint = {2008.10682},
timestamp = {Fri, 28 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2008-10682.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2009-09009,
author = {Vidya A. Chhabria and
Vipul Ahuja and
Ashwath Prabhu and
Nikhil Patil and
Palkesh Jain and
Sachin S. Sapatnekar},
title = {Thermal and {IR} Drop Analysis Using Convolutional Encoder-Decoder
Networks},
journal = {CoRR},
volume = {abs/2009.09009},
year = {2020},
url = {https://arxiv.org/abs/2009.09009},
eprinttype = {arXiv},
eprint = {2009.09009},
timestamp = {Wed, 23 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2009-09009.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2010-00051,
author = {Kishor Kunal and
Jitesh Poojary and
Tonmoy Dhar and
Meghna Madhusudan and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {A general approach for identifying hierarchical symmetry constraints
for analog circuit layout},
journal = {CoRR},
volume = {abs/2010.00051},
year = {2020},
url = {https://arxiv.org/abs/2010.00051},
eprinttype = {arXiv},
eprint = {2010.00051},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2010-00051.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2012-10597,
author = {Vidya A. Chhabria and
Yanqing Zhang and
Haoxing Ren and
Ben Keller and
Brucek Khailany and
Sachin S. Sapatnekar},
title = {{MAVIREC:} ML-Aided Vectored IR-DropEstimation and Classification},
journal = {CoRR},
volume = {abs/2012.10597},
year = {2020},
url = {https://arxiv.org/abs/2012.10597},
eprinttype = {arXiv},
eprint = {2012.10597},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2012-10597.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ZabihiCZKWS19,
author = {Masoud Zabihi and
Zamshed Iqbal Chowdhury and
Zhengyang Zhao and
Ulya R. Karpuzcu and
Jianping Wang and
Sachin S. Sapatnekar},
title = {In-Memory Processing on the Spintronic {CRAM:} From Hardware Design
to Application Mapping},
journal = {{IEEE} Trans. Computers},
volume = {68},
number = {8},
pages = {1159--1173},
year = {2019},
url = {https://doi.org/10.1109/TC.2018.2858251},
doi = {10.1109/TC.2018.2858251},
timestamp = {Thu, 08 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/ZabihiCZKWS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SenguptaSHS19,
author = {Deepashree Sengupta and
Farhana Sharmin Snigdha and
Jiang Hu and
Sachin S. Sapatnekar},
title = {An Analytical Approach for Error {PMF} Characterization in Approximate
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {70--83},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2803626},
doi = {10.1109/TCAD.2018.2803626},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SenguptaSHS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SnigdhaSHS19,
author = {Farhana Sharmin Snigdha and
Deepashree Sengupta and
Jiang Hu and
Sachin S. Sapatnekar},
title = {Dynamic Approximation of {JPEG} Hardware},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {295--308},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808224},
doi = {10.1109/TCAD.2018.2808224},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SnigdhaSHS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiS19,
author = {Tengtao Li and
Sachin S. Sapatnekar},
title = {Stress-Induced Performance Shifts in 3D DRAMs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {24},
number = {5},
pages = {51:1--51:21},
year = {2019},
url = {https://doi.org/10.1145/3331527},
doi = {10.1145/3331527},
timestamp = {Wed, 23 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/LiS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SnigdhaAMMHS19,
author = {Farhana Sharmin Snigdha and
Ibrahim Ahmed and
Susmita Dey Manasi and
Meghna G. Mankalale and
Jiang Hu and
Sachin S. Sapatnekar},
editor = {Toshiyuki Shibuya},
title = {SeFAct: selective feature activation and early classification for
CNNs},
booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019},
pages = {487--492},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3287624.3287663},
doi = {10.1145/3287624.3287663},
timestamp = {Mon, 18 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/SnigdhaAMMHS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AjayiCFHHKKLMNP19,
author = {Tutu Ajayi and
Vidya A. Chhabria and
Mateus Foga{\c{c}}a and
Soheil Hashemi and
Abdelrahman Hosny and
Andrew B. Kahng and
Minsoo Kim and
Jeongsup Lee and
Uday Mallappa and
Marina Neseem and
Geraldo Pradipta and
Sherief Reda and
Mehdi Saligane and
Sachin S. Sapatnekar and
Carl Sechen and
Mohamed Shalan and
William Swartz and
Lutong Wang and
Zhehong Wang and
Mingyu Woo and
Bangqi Xu},
title = {Toward an Open-Source Digital Flow: First Learnings from the OpenROAD
Project},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {76},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3326334},
doi = {10.1145/3316781.3326334},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/AjayiCFHHKKLMNP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KunalMSXBHHKS19,
author = {Kishor Kunal and
Meghna Madhusudan and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Desmond A. Kirkpatrick and
Sachin S. Sapatnekar},
title = {{ALIGN:} Open-Source Analog Layout Automation from the Ground Up},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {77},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3323471},
doi = {10.1145/3316781.3323471},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KunalMSXBHHKS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PerriconeLMNSWH19,
author = {Robert Perricone and
Zhaoxin Liang and
Meghna G. Mankalale and
Michael T. Niemier and
Sachin S. Sapatnekar and
Jianping Wang and
Xiaobo Sharon Hu},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {390--395},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8714916},
doi = {10.23919/DATE.2019.8714916},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PerriconeLMNSWH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZabihiZCRDPKWS19,
author = {Masoud Zabihi and
Zhengyang Zhao and
Zamshed I. Chowdhury and
Salonik Resch and
Mahendra DC and
Thomas Peterson and
Ulya R. Karpuzcu and
Jianping Wang and
Sachin S. Sapatnekar},
editor = {Houman Homayoun and
Baris Taskin and
Tinoosh Mohsenin and
Weisheng Zhao},
title = {True In-memory Computing with the {CRAM:} From Technology to Applications},
booktitle = {Proceedings of the 2019 on Great Lakes Symposium on VLSI, {GLSVLSI}
2019, Tysons Corner, VA, USA, May 9-11, 2019},
pages = {379},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3299874.3319451},
doi = {10.1145/3299874.3319451},
timestamp = {Wed, 10 Mar 2021 14:55:38 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ZabihiZCRDPKWS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipccc/FanLS19,
author = {Qianqian Fan and
David J. Lilja and
Sachin S. Sapatnekar},
title = {Using DCT-based Approximate Communication to Improve {MPI} Performance
in Parallel Clusters},
booktitle = {38th {IEEE} International Performance Computing and Communications
Conference, {IPCCC} 2019, London, United Kingdom, October 29-31, 2019},
pages = {1--10},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/IPCCC47392.2019.8958720},
doi = {10.1109/IPCCC47392.2019.8958720},
timestamp = {Wed, 05 Feb 2020 12:51:53 +0100},
biburl = {https://dblp.org/rec/conf/ipccc/FanLS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irps/DharS19,
author = {Tonmoy Dhar and
Sachin S. Sapatnekar},
title = {Reliability Analysis of a Delay-Locked Loop Under {HCI} and {BTI}
Degradation},
booktitle = {{IEEE} International Reliability Physics Symposium, {IRPS} 2019, Monterey,
CA, USA, March 31 - April 4, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/IRPS.2019.8720447},
doi = {10.1109/IRPS.2019.8720447},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/irps/DharS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/Sapatnekar19,
author = {Sachin S. Sapatnekar},
editor = {Ismail Bustany and
William Swartz},
title = {Electromigration-Aware Interconnect Design},
booktitle = {Proceedings of the 2019 International Symposium on Physical Design,
{ISPD} 2019, San Francisco, CA, USA, April 14-17, 2019},
pages = {83--90},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3299902.3313156},
doi = {10.1145/3299902.3313156},
timestamp = {Thu, 11 Apr 2019 09:48:44 +0200},
biburl = {https://dblp.org/rec/conf/ispd/Sapatnekar19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LiSH19,
author = {Chaofan Li and
Sachin S. Sapatnekar and
Jiang Hu},
title = {Fast Mapping-Based High-Level Synthesis of Pipelined Circuits},
booktitle = {20th International Symposium on Quality Electronic Design, {ISQED}
2019, Santa Clara, CA, USA, March 6-7, 2019},
pages = {33--38},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISQED.2019.8697596},
doi = {10.1109/ISQED.2019.8697596},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/LiSH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ZabihiZMCRPKWS19,
author = {Masoud Zabihi and
Zhengyang Zhao and
D. C. Mahendra and
Zamshed I. Chowdhury and
Salonik Resch and
Thomas Peterson and
Ulya R. Karpuzcu and
Jianping Wang and
Sachin S. Sapatnekar},
title = {Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation
Platform},
booktitle = {20th International Symposium on Quality Electronic Design, {ISQED}
2019, Santa Clara, CA, USA, March 6-7, 2019},
pages = {52--57},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISQED.2019.8697377},
doi = {10.1109/ISQED.2019.8697377},
timestamp = {Tue, 28 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ZabihiZMCRPKWS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChhabriaS19,
author = {Vidya A. Chhabria and
Sachin S. Sapatnekar},
title = {Impact of Self-heating on Performance and Reliability in FinFET and
{GAAFET} Designs},
booktitle = {20th International Symposium on Quality Electronic Design, {ISQED}
2019, Santa Clara, CA, USA, March 6-7, 2019},
pages = {235--240},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISQED.2019.8697786},
doi = {10.1109/ISQED.2019.8697786},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ChhabriaS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/EversonSK19,
author = {Luke R. Everson and
Sachin S. Sapatnekar and
Chris H. Kim},
title = {A 40{\texttimes}40 Four-Neighbor Time-Based In-Memory Computing Graph
{ASIC} Chip Featuring Wavefront Expansion and 2D Gradient Control},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {50--52},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662455},
doi = {10.1109/ISSCC.2019.8662455},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/EversonSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/HuangHSH19,
author = {Lin Huang and
I{-}Hong Hou and
Sachin S. Sapatnekar and
Jiang Hu},
title = {Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors},
booktitle = {25th {IEEE} International Conference on Embedded and Real-Time Computing
Systems and Applications, {RTCSA} 2019, Hangzhou, China, August 18-21,
2019},
pages = {1--11},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/RTCSA.2019.8864597},
doi = {10.1109/RTCSA.2019.8864597},
timestamp = {Mon, 09 Aug 2021 14:54:02 +0200},
biburl = {https://dblp.org/rec/conf/rtcsa/HuangHSH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/19/SenguptaHS19,
author = {Deepashree Sengupta and
Jiang Hu and
Sachin S. Sapatnekar},
editor = {Sherief Reda and
Muhammad Shafique},
title = {Error Analysis and Optimization in Approximate Arithmetic Circuits},
booktitle = {Approximate Circuits, Methodologies and {CAD}},
pages = {225--246},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-319-99322-5\_11},
doi = {10.1007/978-3-319-99322-5\_11},
timestamp = {Sun, 02 Feb 2020 18:57:32 +0100},
biburl = {https://dblp.org/rec/books/sp/19/SenguptaHS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1905-05011,
author = {Susmita Dey Manasi and
Farhana Sharmin Snigdha and
Sachin S. Sapatnekar},
title = {NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning
of {CNN} Computations on Cloud-Connected Mobile Clients},
journal = {CoRR},
volume = {abs/1905.05011},
year = {2019},
url = {http://arxiv.org/abs/1905.05011},
eprinttype = {arXiv},
eprint = {1905.05011},
timestamp = {Tue, 28 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1905-05011.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1908-11373,
author = {Salonik Resch and
S. Karen Khatamifard and
Zamshed Iqbal Chowdhury and
Masoud Zabihi and
Zhengyang Zhao and
Jianping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {A Machine Learning Accelerator In-Memory for Energy Harvesting},
journal = {CoRR},
volume = {abs/1908.11373},
year = {2019},
url = {http://arxiv.org/abs/1908.11373},
eprinttype = {arXiv},
eprint = {1908.11373},
timestamp = {Wed, 04 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1908-11373.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/ChowdhuryHKZLLS18,
author = {Zamshed I. Chowdhury and
Jonathan D. Harms and
S. Karen Khatamifard and
Masoud Zabihi and
Yang Lv and
Andrew Lyle and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu and
Jianping Wang},
title = {Efficient In-Memory Processing Using Spintronics},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {17},
number = {1},
pages = {42--46},
year = {2018},
url = {https://doi.org/10.1109/LCA.2017.2751042},
doi = {10.1109/LCA.2017.2751042},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cal/ChowdhuryHKZLLS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuSH18,
author = {Wenbin Xu and
Sachin S. Sapatnekar and
Jiang Hu},
title = {A Simple Yet Efficient Accuracy-Configurable Adder Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {6},
pages = {1112--1125},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2803081},
doi = {10.1109/TVLSI.2018.2803081},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XuSH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MarellaS18,
author = {Sravan K. Marella and
Sachin S. Sapatnekar},
title = {Circuit Performance Shifts Due to Layout-Dependent Stress in Planar
and 3D-ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2907--2920},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2866290},
doi = {10.1109/TVLSI.2018.2866290},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MarellaS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HuangLSH18,
author = {Lin Huang and
Youmeng Li and
Sachin S. Sapatnekar and
Jiang Hu},
title = {Using imprecise computing for improved non-preemptive real-time scheduling},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {71:1--71:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3196134},
doi = {10.1145/3195970.3196134},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/dac/HuangLSH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/JainSW0R18,
author = {Shubham Jain and
Sachin S. Sapatnekar and
Jianping Wang and
Kaushik Roy and
Anand Raghunathan},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Computing-in-memory with spintronics},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {1640--1645},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342277},
doi = {10.23919/DATE.2018.8342277},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/JainSW0R18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiS18,
author = {Tengtao Li and
Sachin S. Sapatnekar},
editor = {Iris Bahar},
title = {Strain-aware performance evaluation and correction for OTFT-based
flexible displays},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {40},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240853},
doi = {10.1145/3240765.3240853},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LiS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtns/HuangHSH18,
author = {Lin Huang and
I{-}Hong Hou and
Sachin S. Sapatnekar and
Jiang Hu},
editor = {Yassine Ouhammou and
Fr{\'{e}}d{\'{e}}ric Ridouard and
Emmanuel Grolleau and
Mathieu Jan and
Moris Behnam},
title = {Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality
Systems},
booktitle = {Proceedings of the 26th International Conference on Real-Time Networks
and Systems, {RTNS} 2018, Chasseneuil-du-Poitou, France, October 10-12,
2018},
pages = {159--169},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3273905.3273909},
doi = {10.1145/3273905.3273909},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtns/HuangHSH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smacd/UrbanSS18,
author = {Marcel Urban and
Sachin S. Sapatnekar and
Richard Shi},
title = {Plenaries},
booktitle = {15th International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design, {SMACD} 2018,
Prague, Czech Republic, July 2-5, 2018},
pages = {1--2},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/SMACD.2018.8434922},
doi = {10.1109/SMACD.2018.8434922},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/smacd/UrbanSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1811-02016,
author = {Meghna G. Mankalale and
Zhengyang Zhao and
Jianping Wang and
Sachin S. Sapatnekar},
title = {SkyLogic - {A} proposal for a skyrmion logic device},
journal = {CoRR},
volume = {abs/1811.02016},
year = {2018},
url = {http://arxiv.org/abs/1811.02016},
eprinttype = {arXiv},
eprint = {1811.02016},
timestamp = {Tue, 28 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1811-02016.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1812-03989,
author = {Salonik Resch and
S. Karen Khatamifard and
Zamshed Iqbal Chowdhury and
Masoud Zabihi and
Zhengyang Zhao and
Jianping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {Exploiting Processing in Non-Volatile Memory for Binary Neural Network
Accelerators},
journal = {CoRR},
volume = {abs/1812.03989},
year = {2018},
url = {http://arxiv.org/abs/1812.03989},
eprinttype = {arXiv},
eprint = {1812.03989},
timestamp = {Tue, 28 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1812-03989.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1812-08918,
author = {Zamshed I. Chowdhury and
S. Karen Khatamifard and
Zhengyang Zhao and
Masoud Zabihi and
Salonik Resch and
Meisam Razaviyayn and
Jianping Wang and
Sachin S. Sapatnekar and
Ulya R. Karpuzcu},
title = {Computational {RAM} to Accelerate String Matching at Scale},
journal = {CoRR},
volume = {abs/1812.08918},
year = {2018},
url = {http://arxiv.org/abs/1812.08918},
eprinttype = {arXiv},
eprint = {1812.08918},
timestamp = {Tue, 28 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1812-08918.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MishraS17,
author = {Vivek Mishra and
Sachin S. Sapatnekar},
title = {Probabilistic Wire Resistance Degradation Due to Electromigration
in Power Grids},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {4},
pages = {628--640},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2016.2584054},
doi = {10.1109/TCAD.2016.2584054},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MishraS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SenguptaS17,
author = {Deepashree Sengupta and
Sachin S. Sapatnekar},
title = {Estimating Circuit Aging Due to {BTI} and {HCI} Using Ring-Oscillator-Based
Sensors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {10},
pages = {1688--1701},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2017.2648840},
doi = {10.1109/TCAD.2017.2648840},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SenguptaS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JainMS17,
author = {Palkesh Jain and
Vivek Mishra and
Sachin S. Sapatnekar},
title = {Fast Stochastic Analysis of Electromigration in Power Distribution
Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2512--2524},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2706520},
doi = {10.1109/TVLSI.2017.2706520},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JainMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/LiSSXHS17,
author = {Chaofan Li and
Deepashree Sengupta and
Farhana Sharmin Snigdha and
Wenbin Xu and
Jiang Hu and
Sachin S. Sapatnekar},
title = {A quantifiable approach to approximate computing: special session},
booktitle = {Proceedings of the 2017 International Conference on Compilers, Architectures
and Synthesis for Embedded Systems, {CASES} 2017, Seoul, Republic
of Korea, October 15-20, 2017},
pages = {1:1--1:2},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3125501.3125511},
doi = {10.1145/3125501.3125511},
timestamp = {Thu, 11 Mar 2021 17:04:51 +0100},
biburl = {https://dblp.org/rec/conf/cases/LiSSXHS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WangSKCKD0RHNNC17,
author = {Jianping Wang and
Sachin S. Sapatnekar and
Chris H. Kim and
Paul A. Crowell and
Steven J. Koester and
Supriyo Datta and
Kaushik Roy and
Anand Raghunathan and
Xiaobo Sharon Hu and
Michael T. Niemier and
Azad Naeemi and
Chia{-}Ling Chien and
Caroline A. Ross and
Roland Kawakami},
title = {A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {16:1--16:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3072942},
doi = {10.1145/3061639.3072942},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WangSKCKD0RHNNC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MishraJMS17,
author = {Vivek Mishra and
Palkesh Jain and
Sravan K. Marella and
Sachin S. Sapatnekar},
title = {Incorporating the Role of Stress on Electromigration in Power Grids
with Via Arrays},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {21:1--21:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062266},
doi = {10.1145/3061639.3062266},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MishraJMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SenguptaSHS17,
author = {Deepashree Sengupta and
Farhana Sharmin Snigdha and
Jiang Hu and
Sachin S. Sapatnekar},
title = {{SABER:} Selection of Approximate Bits for the Design of Error Tolerant
Circuits},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {72:1--72:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062314},
doi = {10.1145/3061639.3062314},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SenguptaSHS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PerriconeALMHKN17,
author = {Robert Perricone and
Ibrahim Ahmed and
Zhaoxin Liang and
Meghna G. Mankalale and
Xiaobo Sharon Hu and
Chris H. Kim and
Michael T. Niemier and
Sachin S. Sapatnekar and
Jianping Wang},
editor = {David Atienza and
Giorgio Di Natale},
title = {Advanced spintronic memory and logic for non-volatile processors},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {972--977},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927132},
doi = {10.23919/DATE.2017.7927132},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/PerriconeALMHKN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiS17,
author = {Tengtao Li and
Sachin S. Sapatnekar},
editor = {Sri Parameswaran},
title = {Stress-aware performance evaluation of 3D-stacked wide {I/O} DRAMs},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {645--650},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203838},
doi = {10.1109/ICCAD.2017.8203838},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LiS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/XuSH17,
author = {Wenbin Xu and
Sachin S. Sapatnekar and
Jiang Hu},
title = {A simple yet efficient accuracy configurable adder design},
booktitle = {2017 {IEEE/ACM} International Symposium on Low Power Electronics and
Design, {ISLPED} 2017, Taipei, Taiwan, July 24-26, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISLPED.2017.8009206},
doi = {10.1109/ISLPED.2017.8009206},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/XuSH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/FanSL17,
author = {Qianqian Fan and
Sachin S. Sapatnekar and
David J. Lilja},
title = {Cost-quality trade-offs of approximate memory repair mechanisms for
image data},
booktitle = {18th International Symposium on Quality Electronic Design, {ISQED}
2017, Santa Clara, CA, USA, March 14-15, 2017},
pages = {438--444},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISQED.2017.7918355},
doi = {10.1109/ISQED.2017.7918355},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/FanSL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/MankalaleS16,
author = {Meghna G. Mankalale and
Sachin S. Sapatnekar},
title = {Optimized Standard Cells for All-Spin Logic},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {13},
number = {2},
pages = {21:1--21:22},
year = {2016},
url = {https://doi.org/10.1145/2967612},
doi = {10.1145/2967612},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/MankalaleS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PosserMJRS16,
author = {Gracieli Posser and
Vivek Mishra and
Palkesh Jain and
Ricardo Reis and
Sachin S. Sapatnekar},
title = {Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {2},
pages = {220--231},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2015.2456427},
doi = {10.1109/TCAD.2015.2456427},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PosserMJRS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JainCS16,
author = {Palkesh Jain and
Jordi Cortadella and
Sachin S. Sapatnekar},
title = {A Fast and Retargetable Framework for Logic-IP-Internal Electromigration
Assessment Comprehending Advanced Waveform Effects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {6},
pages = {2345--2358},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2505504},
doi = {10.1109/TVLSI.2015.2505504},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JainCS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiangMBS16,
author = {Zhaoxin Liang and
Meghna G. Mankalale and
Brandon Del Bel and
Sachin S. Sapatnekar},
title = {Logic and memory design using spin-based circuits},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {103--108},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7427996},
doi = {10.1109/ASPDAC.2016.7427996},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiangMBS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/CortadellaLMRS16,
author = {Jordi Cortadella and
Marc Lupon and
Alberto Moreno and
Antoni Roca and
Sachin S. Sapatnekar},
title = {Ring Oscillator Clocks and Margins},
booktitle = {22nd {IEEE} International Symposium on Asynchronous Circuits and Systems,
{ASYNC} 2016, Porto Alegre, Brazil, May 8-11, 2016},
pages = {19--26},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ASYNC.2016.14},
doi = {10.1109/ASYNC.2016.14},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/async/CortadellaLMRS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SenguptaMS16,
author = {Deepashree Sengupta and
Vivek Mishra and
Sachin S. Sapatnekar},
title = {Invited - Optimizing device reliability effects at the intersection
of physics, circuits, and architecture},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {31:1--31:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2905016},
doi = {10.1145/2897937.2905016},
timestamp = {Tue, 06 Nov 2018 16:58:19 +0100},
biburl = {https://dblp.org/rec/conf/dac/SenguptaMS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MishraS16,
author = {Vivek Mishra and
Sachin S. Sapatnekar},
title = {Predicting electromigration mortality under temperature and product
lifetime specifications},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {43:1--43:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898070},
doi = {10.1145/2897937.2898070},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MishraS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SnigdhaSHS16,
author = {Farhana Sharmin Snigdha and
Deepashree Sengupta and
Jiang Hu and
Sachin S. Sapatnekar},
title = {Optimal design of {JPEG} hardware under the approximate computing
paradigm},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {106:1--106:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898057},
doi = {10.1145/2897937.2898057},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SnigdhaSHS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiSH16,
author = {Chaofan Li and
Sachin S. Sapatnekar and
Jiang Hu},
editor = {Frank Liu},
title = {Control synthesis and delay sensor deployment for efficient {ASV}
designs},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
pages = {64},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2966986.2967017},
doi = {10.1145/2966986.2967017},
timestamp = {Fri, 23 Jun 2023 22:29:48 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LiSH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/algo/Sapatnekar16,
author = {Sachin S. Sapatnekar},
title = {Power Grid Analysis},
booktitle = {Encyclopedia of Algorithms},
pages = {1598--1601},
year = {2016},
url = {https://doi.org/10.1007/978-1-4939-2864-4\_740},
doi = {10.1007/978-1-4939-2864-4\_740},
timestamp = {Wed, 12 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/algo/Sapatnekar16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/algo/Sapatnekar16a,
author = {Sachin S. Sapatnekar},
title = {Statistical Timing Analysis},
booktitle = {Encyclopedia of Algorithms},
pages = {2095--2099},
year = {2016},
url = {https://doi.org/10.1007/978-1-4939-2864-4\_742},
doi = {10.1007/978-1-4939-2864-4\_742},
timestamp = {Wed, 12 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/algo/Sapatnekar16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/MankalaleLS16,
author = {Meghna G. Mankalale and
Zhaoxin Liang and
Sachin S. Sapatnekar},
title = {{STEM:} {A} Scheme for Two-phase Evaluation of Majority Logic},
journal = {CoRR},
volume = {abs/1609.05141},
year = {2016},
url = {http://arxiv.org/abs/1609.05141},
eprinttype = {arXiv},
eprint = {1609.05141},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/MankalaleLS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/MankalaleLZKWS16,
author = {Meghna G. Mankalale and
Zhaoxin Liang and
Zhengyang Zhao and
Chris H. Kim and
Jianping Wang and
Sachin S. Sapatnekar},
title = {CoMET: Composite-Input Magnetoelectric-based Logic Technology},
journal = {CoRR},
volume = {abs/1611.09714},
year = {2016},
url = {http://arxiv.org/abs/1611.09714},
eprinttype = {arXiv},
eprint = {1611.09714},
timestamp = {Tue, 28 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/MankalaleLZKWS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/KimPCKSWK15,
author = {Jongyeon Kim and
Ayan Paul and
Paul A. Crowell and
Steven J. Koester and
Sachin S. Sapatnekar and
Jianping Wang and
Chris H. Kim},
title = {Spin-Based Computing: Device Concepts, Current Status, and a Case
Study on a High-Performance Microprocessor},
journal = {Proc. {IEEE}},
volume = {103},
number = {1},
pages = {106--130},
year = {2015},
url = {https://doi.org/10.1109/JPROC.2014.2361767},
doi = {10.1109/JPROC.2014.2361767},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pieee/KimPCKSWK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/CortadellaOKS15,
author = {Jordi Cortadella and
Marc Galceran Oms and
Michael Kishinevsky and
Sachin S. Sapatnekar},
title = {{RTL} Synthesis: From Logic Synthesis to Automatic Pipelining},
journal = {Proc. {IEEE}},
volume = {103},
number = {11},
pages = {2061--2075},
year = {2015},
url = {https://doi.org/10.1109/JPROC.2015.2456189},
doi = {10.1109/JPROC.2015.2456189},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pieee/CortadellaOKS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MarellaS15,
author = {Sravan K. Marella and
Sachin S. Sapatnekar},
title = {A Holistic Analysis of Circuit Performance Variations in 3-D ICs With
Thermal and TSV-Induced Stress Considerations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {7},
pages = {1308--1321},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2335154},
doi = {10.1109/TVLSI.2014.2335154},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MarellaS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/JainSC15,
author = {Palkesh Jain and
Sachin S. Sapatnekar and
Jordi Cortadella},
title = {A retargetable and accurate methodology for logic-IP-internal electromigration
assessment},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {346--351},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7059029},
doi = {10.1109/ASPDAC.2015.7059029},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/JainSC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiLSH15,
author = {Chaofan Li and
Wei Luo and
Sachin S. Sapatnekar and
Jiang Hu},
title = {Joint precision optimization and high level synthesis for approximate
computing},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {104:1--104:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2744863},
doi = {10.1145/2744769.2744863},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiLSH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SenguptaS15,
author = {Deepashree Sengupta and
Sachin S. Sapatnekar},
editor = {Diana Marculescu and
Frank Liu},
title = {{FEMTO:} Fast Error Analysis in Multipliers through Topological Traversal},
booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
pages = {294--299},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCAD.2015.7372583},
doi = {10.1109/ICCAD.2015.7372583},
timestamp = {Mon, 26 Jun 2023 16:43:56 +0200},
biburl = {https://dblp.org/rec/conf/iccad/SenguptaS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MarellaTMS15,
author = {Sravan K. Marella and
Amit Ranjan Trivedi and
Saibal Mukhopadhyay and
Sachin S. Sapatnekar},
editor = {Diana Marculescu and
Frank Liu},
title = {Optimization of FinFET-based circuits using a dual gate pitch technique},
booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
pages = {758--763},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCAD.2015.7372646},
doi = {10.1109/ICCAD.2015.7372646},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MarellaTMS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/CortadellaLLLMR15,
author = {Jordi Cortadella and
Luciano Lavagno and
Pedro Lopez and
Marc Lupon and
Alberto Moreno and
Antoni Roca and
Sachin S. Sapatnekar},
title = {Reactive clocks with variability-tracking jitter},
booktitle = {33rd {IEEE} International Conference on Computer Design, {ICCD} 2015,
New York City, NY, USA, October 18-21, 2015},
pages = {511--518},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ICCD.2015.7357159},
doi = {10.1109/ICCD.2015.7357159},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccd/CortadellaLLLMR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PosserMJRS15,
author = {Gracieli Posser and
Vivek Mishra and
Palkesh Jain and
Ricardo Reis and
Sachin S. Sapatnekar},
title = {Impact on performance, power, area and wirelength using electromigration-aware
cells},
booktitle = {2015 {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2015, Cairo, Egypt, December 6-9, 2015},
pages = {129--132},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICECS.2015.7440266},
doi = {10.1109/ICECS.2015.7440266},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/PosserMJRS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irps/JainSC15,
author = {Palkesh Jain and
Sachin S. Sapatnekar and
Jordi Cortadella},
title = {Stochastic and topologically aware electromigration analysis for clock
skew},
booktitle = {{IEEE} International Reliability Physics Symposium, {IRPS} 2015, Monterey,
CA, USA, April 19-23, 2015},
pages = {3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/IRPS.2015.7112714},
doi = {10.1109/IRPS.2015.7112714},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/irps/JainSC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irps/MishraS15,
author = {Vivek Mishra and
Sachin S. Sapatnekar},
title = {Circuit delay variability due to wire resistance evolution under {AC}
electromigration},
booktitle = {{IEEE} International Reliability Physics Symposium, {IRPS} 2015, Monterey,
CA, USA, April 19-23, 2015},
pages = {3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/IRPS.2015.7112713},
doi = {10.1109/IRPS.2015.7112713},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/irps/MishraS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/PosserPMJRS15,
author = {Gracieli Posser and
Lucas de Paris and
Vivek Mishra and
Palkesh Jain and
Ricardo Reis and
Sachin S. Sapatnekar},
title = {Reducing the signal Electromigration effects on different logic gates
by cell layout optimization},
booktitle = {{IEEE} 6th Latin American Symposium on Circuits {\&} Systems,
{LASCAS} 2015, Montevideo, Uruguay, February 24-27, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/LASCAS.2015.7250429},
doi = {10.1109/LASCAS.2015.7250429},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/lascas/PosserPMJRS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/WeiSVLARHTKS14,
author = {Yaoguang Wei and
Cliff C. N. Sze and
Natarajan Viswanathan and
Zhuo Li and
Charles J. Alpert and
Lakshmi N. Reddy and
Andrew D. Huber and
Gustavo E. T{\'{e}}llez and
Douglas Keller and
Sachin S. Sapatnekar},
title = {Techniques for scalable and effective routability evaluation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {19},
number = {2},
pages = {17:1--17:37},
year = {2014},
url = {https://doi.org/10.1145/2566663},
doi = {10.1145/2566663},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/WeiSVLARHTKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BoghratiS14,
author = {Baktash Boghrati and
Sachin S. Sapatnekar},
title = {Incremental Analysis of Power Grids Using Backward Random Walks},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {19},
number = {3},
pages = {31:1--31:29},
year = {2014},
url = {https://doi.org/10.1145/2611763},
doi = {10.1145/2611763},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/BoghratiS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuptaS14,
author = {Saket Gupta and
Sachin S. Sapatnekar},
title = {Variation-Aware Variable Latency Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {5},
pages = {1106--1117},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2265662},
doi = {10.1109/TVLSI.2013.2265662},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuptaS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouPKS14,
author = {Pingqiang Zhou and
Ayan Paul and
Chris H. Kim and
Sachin S. Sapatnekar},
title = {Distributed On-Chip Switched-Capacitor {DC-DC} Converters Supporting
{DVFS} in Multicore Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {9},
pages = {1954--1967},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2280139},
doi = {10.1109/TVLSI.2013.2280139},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouPKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangS14,
author = {Jianxin Fang and
Sachin S. Sapatnekar},
title = {Incorporating Hot-Carrier Injection Effects Into Timing Analysis for
Large Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {12},
pages = {2738--2751},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2296499},
doi = {10.1109/TVLSI.2013.2296499},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FangS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SenguptaS14,
author = {Deepashree Sengupta and
Sachin S. Sapatnekar},
title = {Predicting circuit aging using ring oscillators},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {430--435},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742929},
doi = {10.1109/ASPDAC.2014.6742929},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SenguptaS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BelKKS14,
author = {Brandon Del Bel and
Jongyeon Kim and
Chris H. Kim and
Sachin S. Sapatnekar},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Improving {STT-MRAM} density through multibit error correction},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--6},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.195},
doi = {10.7873/DATE.2014.195},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/BelKKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PosserMJRS14,
author = {Gracieli Posser and
Vivek Mishra and
Palkesh Jain and
Ricardo Reis and
Sachin S. Sapatnekar},
editor = {Yao{-}Wen Chang},
title = {A systematic approach for analyzing and optimizing cell-internal signal
electromigration},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2014, San Jose, CA, USA, November 3-6, 2014},
pages = {486--491},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICCAD.2014.7001395},
doi = {10.1109/ICCAD.2014.7001395},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/PosserMJRS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SenguptaS14,
author = {Deepashree Sengupta and
Sachin S. Sapatnekar},
editor = {Yao{-}Wen Chang},
title = {ReSCALE: recalibrating sensor circuits for aging and lifetime estimation
under {BTI}},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2014, San Jose, CA, USA, November 3-6, 2014},
pages = {492--497},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICCAD.2014.7001396},
doi = {10.1109/ICCAD.2014.7001396},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SenguptaS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PosserMRS14,
author = {Gracieli Posser and
Vivek Mishra and
Ricardo Augusto da Luz Reis and
Sachin S. Sapatnekar},
title = {Analyzing the electromigration effects on different metal layers and
different wire lengths},
booktitle = {21st {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2014, Marseille, France, December 7-10, 2014},
pages = {682--685},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICECS.2014.7050077},
doi = {10.1109/ICECS.2014.7050077},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/PosserMRS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/YinZSZ14,
author = {Jieming Yin and
Pingqiang Zhou and
Sachin S. Sapatnekar and
Antonia Zhai},
title = {Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for
Heterogeneous Multicore Systems},
booktitle = {2014 {IEEE} 28th International Parallel and Distributed Processing
Symposium, Phoenix, AZ, USA, May 19-23, 2014},
pages = {293--303},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/IPDPS.2014.40},
doi = {10.1109/IPDPS.2014.40},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/YinZSZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PaulKSKK14,
author = {Ayan Paul and
Chaitanya Kshirsagar and
Sachin S. Sapatnekar and
Steven J. Koester and
Chris H. Kim},
title = {Leakage Modeling for Devices with Steep Sub-threshold Slope Considering
Random Threshold Variations},
booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014,
and 2014 13th International Conference on Embedded Systems, Mumbai,
India, January 5-9, 2014},
pages = {399--404},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VLSID.2014.75},
doi = {10.1109/VLSID.2014.75},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PaulKSKK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sapatnekar13,
author = {Sachin S. Sapatnekar},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {1},
pages = {1},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2012.2233032},
doi = {10.1109/TCAD.2012.2233032},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sapatnekar13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sapatnekar13a,
author = {Sachin S. Sapatnekar},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {12},
pages = {1837--1838},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2013.2290171},
doi = {10.1109/TCAD.2013.2290171},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sapatnekar13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/GuptaS13,
author = {Saket Gupta and
Sachin S. Sapatnekar},
title = {Employing circadian rhythms to enhance power and reliability},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {18},
number = {3},
pages = {38:1--38:23},
year = {2013},
url = {https://doi.org/10.1145/2491477.2491482},
doi = {10.1145/2491477.2491482},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/GuptaS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MishraS13,
author = {Vivek Mishra and
Sachin S. Sapatnekar},
title = {The impact of electromigration in copper interconnects on power grid
integrity},
booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin,
TX, USA, May 29 - June 07, 2013},
pages = {88:1--88:6},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2463209.2488842},
doi = {10.1145/2463209.2488842},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MishraS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ZhouMS13,
author = {Pingqiang Zhou and
Vivek Mishra and
Sachin S. Sapatnekar},
editor = {Enrico Macii},
title = {Placement optimization of power supply pads based on locality},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1655--1660},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.335},
doi = {10.7873/DATE.2013.335},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/ZhouMS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WeiLSHAS13,
author = {Yaoguang Wei and
Zhuo Li and
Cliff C. N. Sze and
Shiyan Hu and
Charles J. Alpert and
Sachin S. Sapatnekar},
editor = {Enrico Macii},
title = {{CATALYST:} planning layer directives for effective design closure},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1873--1878},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.373},
doi = {10.7873/DATE.2013.373},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/WeiLSHAS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MarellaS13,
author = {Sravan K. Marella and
Sachin S. Sapatnekar},
editor = {J{\"{o}}rg Henkel},
title = {The impact of shallow trench isolation effects on circuit performance},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
pages = {289--294},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ICCAD.2013.6691134},
doi = {10.1109/ICCAD.2013.6691134},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/MarellaS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/Sapatnekar13,
author = {Sachin S. Sapatnekar},
title = {What happens when circuits grow old: Aging issues in {CMOS} design},
booktitle = {2013 International Symposium on {VLSI} Design, Automation, and Test,
{VLSI-DAT} 2013, Hsinchu, Taiwan, April 22-24, 2013},
pages = {1--2},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLDI-DAT.2013.6533827},
doi = {10.1109/VLDI-DAT.2013.6533827},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/Sapatnekar13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/KeaneKLS12,
author = {John Keane and
Chris H. Kim and
Qunzeng Liu and
Sachin S. Sapatnekar},
title = {Process and Reliability Sensors for Nanoscale {CMOS}},
journal = {{IEEE} Des. Test Comput.},
volume = {29},
number = {5},
pages = {8--17},
year = {2012},
url = {https://doi.org/10.1109/MDT.2012.2211561},
doi = {10.1109/MDT.2012.2211561},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/KeaneKLS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sapatnekar12,
author = {Sachin S. Sapatnekar},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {1},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2178171},
doi = {10.1109/TCAD.2011.2178171},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sapatnekar12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ZhouYS12,
author = {Pingqiang Zhou and
Ping{-}Hung Yuh and
Sachin S. Sapatnekar},
title = {Optimized 3D Network-on-Chip Design Using Simulated Allocation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {17},
number = {2},
pages = {12:1--12:19},
year = {2012},
url = {https://doi.org/10.1145/2159542.2159544},
doi = {10.1145/2159542.2159544},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ZhouYS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/QianSK12,
author = {Haifeng Qian and
Sachin S. Sapatnekar and
Eren Kursun},
title = {Fast poisson solvers for thermal analysis},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {17},
number = {3},
pages = {32:1--32:23},
year = {2012},
url = {https://doi.org/10.1145/2209291.2209305},
doi = {10.1145/2209291.2209305},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/QianSK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangS12,
author = {Jianxin Fang and
Sachin S. Sapatnekar},
title = {Scalable Methods for Analyzing the Circuit Failure Probability Due
to Gate Oxide Breakdown},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {1960--1973},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2166568},
doi = {10.1109/TVLSI.2011.2166568},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FangS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuptaS12,
author = {Saket Gupta and
Sachin S. Sapatnekar},
title = {Compact Current Source Models for Timing Analysis Under Temperature
and Body Bias Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2104--2117},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2169686},
doi = {10.1109/TVLSI.2011.2169686},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuptaS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/BoghratiS12,
author = {Baktash Boghrati and
Sachin S. Sapatnekar},
title = {Incremental power network analysis using backward random walks},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {41--46},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6164983},
doi = {10.1109/ASPDAC.2012.6164983},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/BoghratiS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GuptaS12,
author = {Saket Gupta and
Sachin S. Sapatnekar},
title = {{GNOMO:} Greater-than-NOMinal Vdd operation for {BTI} mitigation},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {271--276},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6164957},
doi = {10.1109/ASPDAC.2012.6164957},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/GuptaS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FangS12,
author = {Jianxin Fang and
Sachin S. Sapatnekar},
title = {The impact of hot carriers on timing in large circuits},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {591--596},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6165025},
doi = {10.1109/ASPDAC.2012.6165025},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/FangS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GuptaS12a,
author = {Saket Gupta and
Sachin S. Sapatnekar},
title = {BTI-aware design using variable latency units},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {775--780},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6165059},
doi = {10.1109/ASPDAC.2012.6165059},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/GuptaS12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/PaulAGVASK12,
author = {Ayan Paul and
Matt Amrein and
Saket Gupta and
Arvind Vinod and
Abhishek Arun and
Sachin S. Sapatnekar and
Chris H. Kim},
title = {Staggered Core Activation: {A} circuit/architectural approach for
mitigating resonant supply noise issues in multi-core multi-power
domain processors},
booktitle = {Proceedings of the {IEEE} 2012 Custom Integrated Circuits Conference,
{CICC} 2012, San Jose, CA, USA, September 9-12, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/CICC.2012.6330673},
doi = {10.1109/CICC.2012.6330673},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/PaulAGVASK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WeiSVLARHTKS12,
author = {Yaoguang Wei and
Cliff C. N. Sze and
Natarajan Viswanathan and
Zhuo Li and
Charles J. Alpert and
Lakshmi N. Reddy and
Andrew D. Huber and
Gustavo E. T{\'{e}}llez and
Douglas Keller and
Sachin S. Sapatnekar},
editor = {Patrick Groeneveld and
Donatella Sciuto and
Soha Hassoun},
title = {{GLARE:} global and local wiring aware routability evaluation},
booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
Francisco, CA, USA, June 3-7, 2012},
pages = {768--773},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2228360.2228499},
doi = {10.1145/2228360.2228499},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/WeiSVLARHTKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/FangGKMMZS12,
author = {Jianxin Fang and
Saket Gupta and
Sanjay V. Kumar and
Sravan K. Marella and
Vivek Mishra and
Pingqiang Zhou and
Sachin S. Sapatnekar},
editor = {Alan J. Hu},
title = {Circuit reliability: From Physics to Architectures: Embedded tutorial
paper},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {243--246},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429431},
doi = {10.1145/2429384.2429431},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/FangGKMMZS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhouCKKS12,
author = {Pingqiang Zhou and
Won Ho Choi and
Bongjin Kim and
Chris H. Kim and
Sachin S. Sapatnekar},
editor = {Alan J. Hu},
title = {Optimization of on-chip switched-capacitor {DC-DC} converters for
high-performance applications},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {263--270},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429435},
doi = {10.1145/2429384.2429435},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ZhouCKKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MarellaKS12,
author = {Sravan K. Marella and
Sanjay V. Kumar and
Sachin S. Sapatnekar},
editor = {Alan J. Hu},
title = {A holistic analysis of circuit timing variations in 3D-ICs with thermal
and TSV-induced stress considerations},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {317--324},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429450},
doi = {10.1145/2429384.2429450},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/MarellaKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isgt/KumaraguruparanSS12,
author = {N. Kumaraguruparan and
H. Sivaramakrishnan and
Sachin S. Sapatnekar},
title = {Residential task scheduling under dynamic pricing using the multiple
knapsack method},
booktitle = {{IEEE} {PES} Innovative Smart Grid Technologies Conference, {ISGT}
2012, Washington, DC, USA, January 16-20, 2012},
pages = {1--6},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISGT.2012.6175656},
doi = {10.1109/ISGT.2012.6175656},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/isgt/KumaraguruparanSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/YinZHSZ12,
author = {Jieming Yin and
Pingqiang Zhou and
Anup Holey and
Sachin S. Sapatnekar and
Antonia Zhai},
editor = {Naresh R. Shanbhag and
Massimo Poncino and
Pai H. Chou and
Ajith Amerasekera},
title = {Energy-efficient non-minimal path on-chip interconnection network
for heterogeneous systems},
booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'12,
Redondo Beach, CA, {USA} - July 30 - August 01, 2012},
pages = {57--62},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2333660.2333675},
doi = {10.1145/2333660.2333675},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/YinZHSZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/Sapatnekar11,
author = {Sachin S. Sapatnekar},
title = {Overcoming Variations in Nanometer-Scale Technologies},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {1},
number = {1},
pages = {5--18},
year = {2011},
url = {https://doi.org/10.1109/JETCAS.2011.2138250},
doi = {10.1109/JETCAS.2011.2138250},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esticas/Sapatnekar11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sapatnekar11,
author = {Sachin S. Sapatnekar},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {1},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097013},
doi = {10.1109/TCAD.2010.2097013},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sapatnekar11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarKS11,
author = {Sanjay V. Kumar and
Chris H. Kim and
Sachin S. Sapatnekar},
title = {Adaptive Techniques for Overcoming Performance Degradation Due to
Aging in {CMOS} Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {4},
pages = {603--614},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2036628},
doi = {10.1109/TVLSI.2009.2036628},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarKS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FangS11,
author = {Jianxin Fang and
Sachin S. Sapatnekar},
title = {Accounting for inherent circuit resilience and process variations
in analyzing gate oxide reliability},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {689--694},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722275},
doi = {10.1109/ASPDAC.2011.5722275},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/FangS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ZhouJKS11,
author = {Pingqiang Zhou and
Dong Jiao and
Chris H. Kim and
Sachin S. Sapatnekar},
editor = {Rakesh Patel and
Tom Andre and
Aurangzeb Khan},
title = {Exploration of on-chip switched-capacitor {DC-DC} converter for multicore
processors using a distributed power delivery network},
booktitle = {2011 {IEEE} Custom Integrated Circuits Conference, {CICC} 2011, San
Jose, CA, USA, Sept. 19-21, 2011},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/CICC.2011.6055333},
doi = {10.1109/CICC.2011.6055333},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ZhouJKS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KungHSS11,
author = {Jaeha Kung and
Inhak Han and
Sachin S. Sapatnekar and
Youngsoo Shin},
editor = {Leon Stok and
Nikil D. Dutt and
Soha Hassoun},
title = {Thermal signature: a simple yet accurate thermal index for floorplan
optimization},
booktitle = {Proceedings of the 48th Design Automation Conference, {DAC} 2011,
San Diego, California, USA, June 5-10, 2011},
pages = {108--113},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2024724.2024748},
doi = {10.1145/2024724.2024748},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KungHSS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BoghratiS11,
author = {Baktash Boghrati and
Sachin S. Sapatnekar},
title = {A scaled random walk solver for fast power grid analysis},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {38--43},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763013},
doi = {10.1109/DATE.2011.5763013},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BoghratiS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KolpeZS11,
author = {T. Kolpe and
Antonia Zhai and
Sachin S. Sapatnekar},
title = {Enabling improved power management in multicore processors through
clustered {DVFS}},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {293--298},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763052},
doi = {10.1109/DATE.2011.5763052},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KolpeZS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/Sapatnekar11,
author = {Sachin S. Sapatnekar},
editor = {Naehyuck Chang and
Hiroshi Nakamura and
Koji Inoue and
Kenichi Osada and
Massimo Poncino},
title = {The whys and hows of thermal management},
booktitle = {Proceedings of the 2011 International Symposium on Low Power Electronics
and Design, 2011, Fukuoka, Japan, August 1-3, 2011},
pages = {283--284},
publisher = {{IEEE/ACM}},
year = {2011},
url = {http://portal.acm.org/citation.cfm?id=2016866\&\#38;CFID=34981777\&\#38;CFTOKEN=25607807},
timestamp = {Mon, 13 Aug 2012 09:40:34 +0200},
biburl = {https://dblp.org/rec/conf/islped/Sapatnekar11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ZhouYZS11,
author = {Pingqiang Zhou and
Jieming Yin and
Antonia Zhai and
Sachin S. Sapatnekar},
editor = {Naehyuck Chang and
Hiroshi Nakamura and
Koji Inoue and
Kenichi Osada and
Massimo Poncino},
title = {NoC frequency scaling with flexible-pipeline routers},
booktitle = {Proceedings of the 2011 International Symposium on Low Power Electronics
and Design, 2011, Fukuoka, Japan, August 1-3, 2011},
pages = {403--408},
publisher = {{IEEE/ACM}},
year = {2011},
url = {http://portal.acm.org/citation.cfm?id=2016897\&\#38;CFID=34981777\&\#38;CFTOKEN=25607807},
timestamp = {Mon, 13 Aug 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/ZhouYZS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/daglib/p/Sapatnekar11,
author = {Sachin S. Sapatnekar},
editor = {Swarup Bhunia and
Saibal Mukhopadhyay},
title = {Statistical Design of Integrated Circuits},
booktitle = {Low-Power Variation-Tolerant Design in Nanometer Silicon},
pages = {109--149},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-1-4419-7418-1\_4},
doi = {10.1007/978-1-4419-7418-1\_4},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/books/daglib/p/Sapatnekar11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sapatnekar10,
author = {Sachin S. Sapatnekar},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {1},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2037282},
doi = {10.1109/TCAD.2009.2037282},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sapatnekar10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuS10,
author = {Qunzeng Liu and
Sachin S. Sapatnekar},
title = {Capturing Post-Silicon Variations Using a Representative Critical
Path},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {211--222},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035552},
doi = {10.1109/TCAD.2009.2035552},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GuptaS10,
author = {Saket Gupta and
Sachin S. Sapatnekar},
title = {Current source modeling in the presence of body bias},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {199--204},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419896},
doi = {10.1109/ASPDAC.2010.5419896},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/GuptaS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhouYS10,
author = {Pingqiang Zhou and
Ping{-}Hung Yuh and
Sachin S. Sapatnekar},
title = {Application-specific 3D Network-on-Chip design using simulated allocation},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {517--522},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419830},
doi = {10.1109/ASPDAC.2010.5419830},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ZhouYS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WeiHLS10,
author = {Yaoguang Wei and
Jiang Hu and
Frank Liu and
Sachin S. Sapatnekar},
title = {Physical design techniques for optimizing RTA-induced variations},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {745--750},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419789},
doi = {10.1109/ASPDAC.2010.5419789},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WeiHLS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/BoghratiS10,
author = {Baktash Boghrati and
Sachin S. Sapatnekar},
title = {Incremental solution of power grids using random walks},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {757--762},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419787},
doi = {10.1109/ASPDAC.2010.5419787},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/BoghratiS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/QianS10,
author = {Haifeng Qian and
Sachin S. Sapatnekar},
editor = {Louis Scheffer and
Joel R. Phillips and
Alan J. Hu},
title = {Fast Poisson solvers for thermal analysis},
booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
San Jose, CA, USA, November 7-11, 2010},
pages = {698--702},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICCAD.2010.5654249},
doi = {10.1109/ICCAD.2010.5654249},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/QianS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/Sapatnekar10,
author = {Sachin S. Sapatnekar},
editor = {Prashant Saxena and
Yao{-}Wen Chang},
title = {Adding a new dimension to physical design},
booktitle = {Proceedings of the 2010 International Symposium on Physical Design,
{ISPD} 2010, San Francisco, California, USA, March 14-17, 2010},
pages = {55},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1735023.1735041},
doi = {10.1145/1735023.1735041},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/Sapatnekar10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/WeiS10,
author = {Yaoguang Wei and
Sachin S. Sapatnekar},
editor = {Prashant Saxena and
Yao{-}Wen Chang},
title = {Dummy fill optimization for enhanced manufacturability},
booktitle = {Proceedings of the 2010 International Symposium on Physical Design,
{ISPD} 2010, San Francisco, California, USA, March 14-17, 2010},
pages = {97--104},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1735023.1735051},
doi = {10.1145/1735023.1735051},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/WeiS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/FangS10,
author = {Jianxin Fang and
Sachin S. Sapatnekar},
title = {Scalable methods for the analysis and optimization of gate oxide breakdown},
booktitle = {11th International Symposium on Quality of Electronic Design {(ISQED}
2010), 22-24 March 2010, San Jose, CA, {USA}},
pages = {638--645},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISQED.2010.5450507},
doi = {10.1109/ISQED.2010.5450507},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/FangS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dac/2010,
editor = {Sachin S. Sapatnekar},
title = {Proceedings of the 47th Design Automation Conference, {DAC} 2010,
Anaheim, California, USA, July 13-18, 2010},
publisher = {{ACM}},
year = {2010},
url = {http://dl.acm.org/citation.cfm?id=1837274},
isbn = {978-1-4503-0002-5},
timestamp = {Wed, 30 Nov 2011 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/2010.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cacm/Sapatnekar09,
author = {Sachin S. Sapatnekar},
title = {Technical perspective - Where the chips may fall},
journal = {Commun. {ACM}},
volume = {52},
number = {8},
pages = {94},
year = {2009},
url = {https://doi.org/10.1145/1536616.1536640},
doi = {10.1145/1536616.1536640},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cacm/Sapatnekar09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/ZhouSS09,
author = {Pingqiang Zhou and
Karthikk Sridharan and
Sachin S. Sapatnekar},
title = {Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity},
journal = {{IEEE} Des. Test Comput.},
volume = {26},
number = {5},
pages = {15--25},
year = {2009},
url = {https://doi.org/10.1109/MDT.2009.120},
doi = {10.1109/MDT.2009.120},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/ZhouSS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MogalQSB09,
author = {Hushrav Mogal and
Haifeng Qian and
Sachin S. Sapatnekar and
Kia Bazargan},
title = {Fast and Accurate Statistical Criticality Computation Under Process
Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {350--363},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013278},
doi = {10.1109/TCAD.2009.2013278},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MogalQSB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuS09,
author = {Qunzeng Liu and
Sachin S. Sapatnekar},
title = {A Framework for Scalable Postsilicon Statistical Delay Prediction
Under Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1201--1212},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021732},
doi = {10.1109/TCAD.2009.2021732},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuhSYC09,
author = {Ping{-}Hung Yuh and
Sachin S. Sapatnekar and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
title = {A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing
Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1295--1306},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2023196},
doi = {10.1109/TCAD.2009.2023196},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuhSYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhouSS09,
author = {Pingqiang Zhou and
Karthikk Sridharan and
Sachin S. Sapatnekar},
editor = {Kazutoshi Wakabayashi},
title = {Congestion-aware power grid optimization for 3D circuits using {MIM}
and {CMOS} decoupling capacitors},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {179--184},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796477},
doi = {10.1109/ASPDAC.2009.4796477},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ZhouSS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KumarKS09,
author = {Sanjay V. Kumar and
Chris H. Kim and
Sachin S. Sapatnekar},
editor = {Kazutoshi Wakabayashi},
title = {Adaptive techniques for overcoming performance degradation due to
aging in digital circuits},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {284--289},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796494},
doi = {10.1109/ASPDAC.2009.4796494},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KumarKS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Sapatnekar09,
author = {Sachin S. Sapatnekar},
editor = {Kazutoshi Wakabayashi},
title = {Addressing thermal and power delivery bottlenecks in 3D circuits},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {423--428},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796518},
doi = {10.1109/ASPDAC.2009.4796518},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/Sapatnekar09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/LiuS09,
author = {Qunzeng Liu and
Sachin S. Sapatnekar},
editor = {Gi{-}Joon Nam and
Prashant Saxena},
title = {Synthesizing a representative critical path for post-silicon delay
prediction},
booktitle = {Proceedings of the 2009 International Symposium on Physical Design,
{ISPD} 2009, San Diego, California, USA, March 29 - April 1, 2009},
pages = {183--190},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1514932.1514973},
doi = {10.1145/1514932.1514973},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/LiuS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Sapatnekar08,
author = {Sachin S. Sapatnekar},
title = {Building your yield of dreams},
journal = {{IEEE} Des. Test Comput.},
volume = {25},
number = {2},
pages = {194--195},
year = {2008},
url = {https://doi.org/10.1109/MDT.2008.31},
doi = {10.1109/MDT.2008.31},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/Sapatnekar08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Sapatnekar08a,
author = {Sachin S. Sapatnekar},
title = {Adapting to the times [review of Adaptive Techniques for Dynamic Processor
Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.;
2008)]},
journal = {{IEEE} Des. Test Comput.},
volume = {25},
number = {5},
pages = {496--497},
year = {2008},
url = {https://doi.org/10.1109/MDT.2008.125},
doi = {10.1109/MDT.2008.125},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/Sapatnekar08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fteda/ZhanKS08,
author = {Yong Zhan and
Sanjay V. Kumar and
Sachin S. Sapatnekar},
title = {Thermally Aware Design},
journal = {Found. Trends Electron. Des. Autom.},
volume = {2},
number = {3},
pages = {255--370},
year = {2008},
url = {https://doi.org/10.1561/1000000007},
doi = {10.1561/1000000007},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/fteda/ZhanKS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangS08,
author = {Tianpei Zhang and
Sachin S. Sapatnekar},
title = {Buffering global interconnects in structured {ASIC} design},
journal = {Integr.},
volume = {41},
number = {2},
pages = {171--182},
year = {2008},
url = {https://doi.org/10.1016/j.vlsi.2007.04.002},
doi = {10.1016/J.VLSI.2007.04.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Sapatnekar08,
author = {Sachin S. Sapatnekar},
title = {Variability and Statistical Design},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {18--32},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.18},
doi = {10.2197/IPSJTSLDM.1.18},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Sapatnekar08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/ZhanS08,
author = {Yong Zhan and
Sachin S. Sapatnekar},
title = {Automated module assignment in stacked-Vdd designs for high-efficiency
power delivery},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {4},
number = {4},
pages = {18:1--18:20},
year = {2008},
url = {https://doi.org/10.1145/1412587.1412591},
doi = {10.1145/1412587.1412591},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/ZhanS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/siamsc/QianS08,
author = {Haifeng Qian and
Sachin S. Sapatnekar},
title = {Stochastic Preconditioning for Diagonally Dominant Matrices},
journal = {{SIAM} J. Sci. Comput.},
volume = {30},
number = {3},
pages = {1178--1204},
year = {2008},
url = {https://doi.org/10.1137/07068713X},
doi = {10.1137/07068713X},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/siamsc/QianS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KarandikarS08,
author = {Shrirang K. Karandikar and
Sachin S. Sapatnekar},
title = {Technology Mapping Using Logical Effort for Solving the Load-Distribution
Problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {45--58},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907067},
doi = {10.1109/TCAD.2007.907067},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KarandikarS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghS08,
author = {Jaskirat Singh and
Sachin S. Sapatnekar},
title = {A Scalable Statistical Static Timing Analyzer Incorporating Correlated
Non-Gaussian and Gaussian Parameter Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {160--173},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907241},
doi = {10.1109/TCAD.2007.907241},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghLS08,
author = {Jaskirat Singh and
Zhi{-}Quan Luo and
Sachin S. Sapatnekar},
title = {A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating
Spatial Correlation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {295--308},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.913391},
doi = {10.1109/TCAD.2007.913391},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghLS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuKSK08,
author = {Jie Gu and
John Keane and
Sachin S. Sapatnekar and
Chris H. Kim},
title = {Statistical Leakage Estimation of Double Gate FinFET Devices Considering
the Width Quantization Property},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {2},
pages = {206--209},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2007.909809},
doi = {10.1109/TVLSI.2007.909809},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuKSK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarKS08,
author = {Sanjay V. Kumar and
Chris H. Kim and
Sachin S. Sapatnekar},
title = {Body Bias Voltage Computations for Process and Temperature Compensation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {3},
pages = {249--262},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2007.912137},
doi = {10.1109/TVLSI.2007.912137},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarKS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KeaneEKSK08,
author = {John Keane and
Hanyong Eom and
Tony Tae{-}Hyoung Kim and
Sachin S. Sapatnekar and
Chris H. Kim},
title = {Stack Sizing for Optimal Current Drivability in Subthreshold Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {5},
pages = {598--602},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.917571},
doi = {10.1109/TVLSI.2008.917571},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KeaneEKSK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SapatnekarHKDKMPS08,
author = {Sachin S. Sapatnekar and
Eshel Haritan and
Kurt Keutzer and
Anirudh Devgan and
Desmond Kirkpatrick and
Stephen Meier and
Duaine Pryor and
Tom Spyrou},
editor = {Limor Fix},
title = {Reinventing {EDA} with manycore processors},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {126--127},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391502},
doi = {10.1145/1391469.1391502},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SapatnekarHKDKMPS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/YuhSYC08,
author = {Ping{-}Hung Yuh and
Sachin S. Sapatnekar and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
editor = {Limor Fix},
title = {A progressive-ILP based routing algorithm for cross-referencing biochips},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {284--289},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391541},
doi = {10.1145/1391469.1391541},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/YuhSYC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KumarKS08,
author = {Sanjay V. Kumar and
Chandramouli V. Kashyap and
Sachin S. Sapatnekar},
editor = {Limor Fix},
title = {A framework for block-based timing sensitivity analysis},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {688--693},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391647},
doi = {10.1145/1391469.1391647},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KumarKS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:reference/crc/2008apda,
editor = {Charles J. Alpert and
Dinesh P. Mehta and
Sachin S. Sapatnekar},
title = {Handbook of Algorithms for Physical Design Automation},
publisher = {Auerbach Publications},
year = {2008},
url = {https://doi.org/10.1201/9781420013481},
doi = {10.1201/9781420013481},
isbn = {978-0-8493-7242-1},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/reference/crc/2008apda.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/crc/AlpertMS08,
author = {Charles J. Alpert and
Dinesh P. Mehta and
Sachin S. Sapatnekar},
editor = {Charles J. Alpert and
Dinesh P. Mehta and
Sachin S. Sapatnekar},
title = {Introduction to Physical Design},
booktitle = {Handbook of Algorithms for Physical Design Automation},
publisher = {Auerbach Publications},
year = {2008},
url = {https://doi.org/10.1201/9781420013481.pt1},
doi = {10.1201/9781420013481.PT1},
timestamp = {Mon, 26 Oct 2020 09:04:39 +0100},
biburl = {https://dblp.org/rec/reference/crc/AlpertMS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/crc/BazarganS08,
author = {Kia Bazargan and
Sachin S. Sapatnekar},
editor = {Charles J. Alpert and
Dinesh P. Mehta and
Sachin S. Sapatnekar},
title = {Physical Design for Three-Dimensional Circuits},
booktitle = {Handbook of Algorithms for Physical Design Automation},
publisher = {Auerbach Publications},
year = {2008},
url = {https://doi.org/10.1201/9781420013481.ch47},
doi = {10.1201/9781420013481.CH47},
timestamp = {Wed, 12 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/crc/BazarganS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/crc/LiuS08,
author = {Frank Liu and
Sachin S. Sapatnekar},
editor = {Charles J. Alpert and
Dinesh P. Mehta and
Sachin S. Sapatnekar},
title = {Metrics Used in Physical Design},
booktitle = {Handbook of Algorithms for Physical Design Automation},
publisher = {Auerbach Publications},
year = {2008},
url = {https://doi.org/10.1201/9781420013481.ch3},
doi = {10.1201/9781420013481.CH3},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/crc/LiuS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0029057,
author = {Prashant Saxena and
Rupesh S. Shelar and
Sachin S. Sapatnekar},
title = {Routing Congestion in {VLSI} Circuits - Estimation and Optimization},
series = {Series on Integrated Circuits and Systems},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/0-387-48550-3},
doi = {10.1007/0-387-48550-3},
isbn = {978-0-387-30037-5},
timestamp = {Tue, 16 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0029057.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Sapatnekar07,
author = {Sachin S. Sapatnekar},
title = {Book Review: An Assay of Biochips},
journal = {{IEEE} Des. Test Comput.},
volume = {24},
number = {4},
pages = {402--403},
year = {2007},
url = {https://doi.org/10.1109/MDT.2007.123},
doi = {10.1109/MDT.2007.123},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/Sapatnekar07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/SapatnekarS07,
author = {Sachin S. Sapatnekar and
Leon Stok},
title = {{DAC} Highlights},
journal = {{IEEE} Des. Test Comput.},
volume = {24},
number = {5},
pages = {502--504},
year = {2007},
url = {https://doi.org/10.1109/MDT.2007.160},
doi = {10.1109/MDT.2007.160},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/SapatnekarS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/ChakrabartyS07,
author = {Krishnendu Chakrabarty and
Sachin S. Sapatnekar},
title = {Editorial to special issue {DAC} 2006},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {3},
number = {3},
pages = {11},
year = {2007},
url = {https://doi.org/10.1145/1295231.1295232},
doi = {10.1145/1295231.1295232},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jetc/ChakrabartyS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VecianaLHMS07,
author = {Gustavo de Veciana and
Marcello Lajolo and
Chen He and
Enrico Macii and
Sachin S. Sapatnekar},
title = {In Memoriam: Margarida F. Jacome},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1549--1550},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.903725},
doi = {10.1109/TCAD.2007.903725},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VecianaLHMS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhanS07,
author = {Yong Zhan and
Sachin S. Sapatnekar},
title = {High-Efficiency Green Function-Based Thermal Simulation Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1661--1675},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895754},
doi = {10.1109/TCAD.2007.895754},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhanS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChangS07,
author = {Hongliang Chang and
Sachin S. Sapatnekar},
title = {Prediction of leakage power under process uncertainties},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {12},
number = {2},
pages = {12},
year = {2007},
url = {https://doi.org/10.1145/1230800.1230804},
doi = {10.1145/1230800.1230804},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ChangS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangS07,
author = {Tianpei Zhang and
Sachin S. Sapatnekar},
title = {Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction
in Global Routing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {15},
number = {6},
pages = {624--636},
year = {2007},
url = {https://doi.org/10.1109/TVLSI.2007.898641},
doi = {10.1109/TVLSI.2007.898641},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GuSK07,
author = {Jie Gu and
Sachin S. Sapatnekar and
Chris H. Kim},
title = {Width-dependent Statistical Leakage Modeling for Random Dopant Induced
Threshold Voltage Shift},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {87--92},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1145/1278480.1278503},
doi = {10.1145/1278480.1278503},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/GuSK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KumarKS07,
author = {Sanjay V. Kumar and
Chris H. Kim and
Sachin S. Sapatnekar},
title = {NBTI-Aware Synthesis of Digital Circuits},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {370--375},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1145/1278480.1278574},
doi = {10.1145/1278480.1278574},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KumarKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuS07,
author = {Qunzeng Liu and
Sachin S. Sapatnekar},
title = {Confidence Scalable Post-Silicon Statistical Delay Prediction under
Process Variations},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {497--502},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1145/1278480.1278609},
doi = {10.1145/1278480.1278609},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiuS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GoplenS07,
author = {Brent Goplen and
Sachin S. Sapatnekar},
title = {Placement of 3D ICs with Thermal and Interlayer Via Considerations},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {626--631},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1145/1278480.1278637},
doi = {10.1145/1278480.1278637},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/GoplenS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MarquesRRSR07,
author = {Felipe S. Marques and
Leomar S. da Rosa Jr. and
Renato P. Ribas and
Sachin S. Sapatnekar and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {{DAG} based library-free technology mapping},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {293--298},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228857},
doi = {10.1145/1228784.1228857},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/MarquesRRSR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Sapatnekar07,
author = {Sachin S. Sapatnekar},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Computer-aided design of 3d integrated circuits},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {317},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228788},
doi = {10.1145/1228784.1228788},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Sapatnekar07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MogalQSB07,
author = {Hushrav Mogal and
Haifeng Qian and
Sachin S. Sapatnekar and
Kia Bazargan},
editor = {Georges G. E. Gielen},
title = {Clustering based pruning for statistical criticality computation under
process variations},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {340--343},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397287},
doi = {10.1109/ICCAD.2007.4397287},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MogalQSB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/BufistovCKS07,
author = {Dmitry Bufistov and
Jordi Cortadella and
Michael Kishinevsky and
Sachin S. Sapatnekar},
editor = {Georges G. E. Gielen},
title = {A general model for performance optimization of sequential systems},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {362--369},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397291},
doi = {10.1109/ICCAD.2007.4397291},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/BufistovCKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhanZS07,
author = {Yong Zhan and
Tianpei Zhang and
Sachin S. Sapatnekar},
editor = {Georges G. E. Gielen},
title = {Module assignment for pin-limited designs under the stacked-Vdd paradigm},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {656--659},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397340},
doi = {10.1109/ICCAD.2007.4397340},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhanZS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LiAQSS07,
author = {Zhuo Li and
Charles J. Alpert and
Stephen T. Quay and
Sachin S. Sapatnekar and
Weiping Shi},
title = {Probabilistic Congestion Prediction with Partial Blockages},
booktitle = {8th International Symposium on Quality of Electronic Design {(ISQED}
2007), 26-28 March 2007, San Jose, CA, {USA}},
pages = {841--846},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISQED.2007.124},
doi = {10.1109/ISQED.2007.124},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/LiAQSS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/SapatnekarM06,
author = {Sachin S. Sapatnekar and
Grant Martin},
title = {{DAC} Highlights},
journal = {{IEEE} Des. Test Comput.},
volume = {23},
number = {3},
pages = {182--184},
year = {2006},
url = {https://doi.org/10.1109/MDT.2006.66},
doi = {10.1109/MDT.2006.66},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/SapatnekarM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Sapatnekar06,
author = {Sachin S. Sapatnekar},
title = {Book Reviews: Plumbing the Depths of Leakage},
journal = {{IEEE} Des. Test Comput.},
volume = {23},
number = {4},
pages = {318--319},
year = {2006},
url = {https://doi.org/10.1109/MDT.2006.87},
doi = {10.1109/MDT.2006.87},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/Sapatnekar06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/TsaiCCGQZKWS06,
author = {Jeng{-}Liang Tsai and
Charlie Chung{-}Ping Chen and
Guoqiang Chen and
Brent Goplen and
Haifeng Qian and
Yong Zhan and
Sung{-}Mo Kang and
Martin D. F. Wong and
Sachin S. Sapatnekar},
title = {Temperature-Aware Placement for SOCs},
journal = {Proc. {IEEE}},
volume = {94},
number = {8},
pages = {1502--1518},
year = {2006},
url = {https://doi.org/10.1109/JPROC.2006.879804},
doi = {10.1109/JPROC.2006.879804},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pieee/TsaiCCGQZKWS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShelarSS06,
author = {Rupesh S. Shelar and
Prashant Saxena and
Sachin S. Sapatnekar},
title = {Technology Mapping Algorithm Targeting Routing Congestion Under Delay
Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {625--636},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870078},
doi = {10.1109/TCAD.2006.870078},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShelarSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghS06,
author = {Jaskirat Singh and
Sachin S. Sapatnekar},
title = {Partition-Based Algorithm for Power Grid Design Using Locality},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {664--677},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870071},
doi = {10.1109/TCAD.2006.870071},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GoplenS06,
author = {Brent Goplen and
Sachin S. Sapatnekar},
title = {Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {692--709},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870069},
doi = {10.1109/TCAD.2006.870069},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GoplenS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertHSS06,
author = {Charles J. Alpert and
Jiang Hu and
Sachin S. Sapatnekar and
Cliff C. N. Sze},
title = {Accurate estimation of global buffer delay within a floorplan},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1140--1145},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855889},
doi = {10.1109/TCAD.2005.855889},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertHSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhanGS06,
author = {Yong Zhan and
Brent Goplen and
Sachin S. Sapatnekar},
editor = {Fumiyasu Hirose},
title = {Electrothermal analysis and optimization techniques for nanoscale
integrated circuits},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {219--222},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594685},
doi = {10.1109/ASPDAC.2006.1594685},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ZhanGS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhangZS06,
author = {Tianpei Zhang and
Yong Zhan and
Sachin S. Sapatnekar},
editor = {Fumiyasu Hirose},
title = {Temperature-aware routing in 3D ICs},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {309--314},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594700},
doi = {10.1109/ASPDAC.2006.1594700},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ZhangZS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KumarKS06,
author = {Sanjay V. Kumar and
Chris H. Kim and
Sachin S. Sapatnekar},
editor = {Fumiyasu Hirose},
title = {Mathematically assisted adaptive body bias {(ABB)} for temperature
compensation in gigascale {LSI} systems},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {559--564},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594744},
doi = {10.1109/ASPDAC.2006.1594744},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KumarKS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhanFS06,
author = {Yong Zhan and
Yan Feng and
Sachin S. Sapatnekar},
editor = {Fumiyasu Hirose},
title = {A fixed-die floorplanning algorithm using an analytical approach},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {771--776},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594779},
doi = {10.1109/ASPDAC.2006.1594779},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ZhanFS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/GuKSK06,
author = {Jie Gu and
John Keane and
Sachin S. Sapatnekar and
Chris H. Kim},
title = {Width Quantization Aware FinFET Circuit Design},
booktitle = {Proceedings of the {IEEE} 2006 Custom Integrated Circuits Conference,
{CICC} 2006, DoubleTree Hotel, San Jose, California, USA, September
10-13, 2006},
pages = {337--340},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/CICC.2006.320916},
doi = {10.1109/CICC.2006.320916},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/GuKSK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SinghS06,
author = {Jaskirat Singh and
Sachin S. Sapatnekar},
editor = {Ellen Sentovich},
title = {Statistical timing analysis with correlated non-gaussian parameters
using independent component analysis},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {155--160},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1146953},
doi = {10.1145/1146909.1146953},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SinghS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KeaneEKSK06,
author = {John Keane and
Hanyong Eom and
Tony Tae{-}Hyoung Kim and
Sachin S. Sapatnekar and
Chris H. Kim},
editor = {Ellen Sentovich},
title = {Subthreshold logical effort: a systematic framework for optimal subthreshold
device sizing},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {425--428},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1147022},
doi = {10.1145/1146909.1147022},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KeaneEKSK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KumarKS06,
author = {Sanjay V. Kumar and
Chris H. Kim and
Sachin S. Sapatnekar},
editor = {Soha Hassoun},
title = {An analytical model for negative bias temperature instability},
booktitle = {2006 International Conference on Computer-Aided Design, {ICCAD} 2006,
San Jose, CA, USA, November 5-9, 2006},
pages = {493--496},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1233501.1233601},
doi = {10.1145/1233501.1233601},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KumarKS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/NookalaLS06,
author = {Vidyasagar Nookala and
David J. Lilja and
Sachin S. Sapatnekar},
editor = {Wolfgang Nebel and
Mircea R. Stan and
Anand Raghunathan and
J{\"{o}}rg Henkel and
Diana Marculescu},
title = {Temperature-aware floorplanning of microarchitecture blocks with IPC-power
dependence modeling and transient analysis},
booktitle = {Proceedings of the 2006 International Symposium on Low Power Electronics
and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006},
pages = {298--303},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1165573.1165644},
doi = {10.1145/1165573.1165644},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/NookalaLS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/NookalaCLS06,
author = {Vidyasagar Nookala and
Ying Chen and
David J. Lilja and
Sachin S. Sapatnekar},
title = {Comparing simulation techniques for microarchitecture-aware floorplanning},
booktitle = {2006 {IEEE} International Symposium on Performance Analysis of Systems
and Software, {ISPASS} 2006, March 19-21, 2006, Austin, Texas, USA,
Proceedings},
pages = {80--88},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISPASS.2006.1620792},
doi = {10.1109/ISPASS.2006.1620792},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispass/NookalaCLS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/BowmanOS06,
author = {Keith A. Bowman and
Michael Orshansky and
Sachin S. Sapatnekar},
title = {Tutorial {II:} Variability and Its Impact on Design},
booktitle = {7th International Symposium on Quality of Electronic Design {(ISQED}
2006), 27-29 March 2006, San Jose, CA, {USA}},
pages = {5},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISQED.2006.141},
doi = {10.1109/ISQED.2006.141},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/BowmanOS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KumarKS06,
author = {Sanjay V. Kumar and
Chris H. Kim and
Sachin S. Sapatnekar},
title = {Impact of {NBTI} on {SRAM} Read Stability and Design for Reliability},
booktitle = {7th International Symposium on Quality of Electronic Design {(ISQED}
2006), 27-29 March 2006, San Jose, CA, {USA}},
pages = {210--218},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISQED.2006.73},
doi = {10.1109/ISQED.2006.73},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/KumarKS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/RosaMCRSR06,
author = {Leomar S. da Rosa Jr. and
Felipe S. Marques and
Tiago Muller Gil Cardoso and
Renato P. Ribas and
Sachin S. Sapatnekar and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {Claudionor Jos{\'{e}} Nunes Coelho Jr. and
Ricardo P. Jacobi and
J{\"{u}}rgen Becker},
title = {Fast disjoint transistor networks from BDDs},
booktitle = {Proceedings of the 19th Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2006, Ouro Preto, MG, Brazil, August 28 -
September 1, 2006},
pages = {137--142},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1150343.1150381},
doi = {10.1145/1150343.1150381},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/RosaMCRSR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Sapatnekar05,
author = {Sachin S. Sapatnekar},
title = {An {EDA} compendium},
journal = {{IEEE} Des. Test Comput.},
volume = {22},
number = {1},
pages = {74--75},
year = {2005},
url = {https://doi.org/10.1109/MDT.2005.3},
doi = {10.1109/MDT.2005.3},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/Sapatnekar05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Sapatnekar05a,
author = {Sachin S. Sapatnekar},
title = {Empowering the designer},
journal = {{IEEE} Des. Test Comput.},
volume = {22},
number = {3},
pages = {280--281},
year = {2005},
url = {https://doi.org/10.1109/MDT.2005.58},
doi = {10.1109/MDT.2005.58},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/Sapatnekar05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/SapatnekarN05,
author = {Sachin S. Sapatnekar and
Kevin J. Nowka},
title = {Guest Editors' Introduction: New Dimensions in 3D Integration},
journal = {{IEEE} Des. Test Comput.},
volume = {22},
number = {6},
pages = {496--497},
year = {2005},
url = {https://doi.org/10.1109/MDT.2005.142},
doi = {10.1109/MDT.2005.142},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/SapatnekarN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/AbabeiFGMZBS05,
author = {Cristinel Ababei and
Yan Feng and
Brent Goplen and
Hushrav Mogal and
Tianpei Zhang and
Kia Bazargan and
Sachin S. Sapatnekar},
title = {Placement and Routing in 3D Integrated Circuits},
journal = {{IEEE} Des. Test Comput.},
volume = {22},
number = {6},
pages = {520--531},
year = {2005},
url = {https://doi.org/10.1109/MDT.2005.150},
doi = {10.1109/MDT.2005.150},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/AbabeiFGMZBS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Sapatnekar05b,
author = {Sachin S. Sapatnekar},
title = {Designing "Vary" Good Circuitry},
journal = {{IEEE} Des. Test Comput.},
volume = {22},
number = {6},
pages = {596--597},
year = {2005},
url = {https://doi.org/10.1109/MDT.2005.137},
doi = {10.1109/MDT.2005.137},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/Sapatnekar05b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QianNS05,
author = {Haifeng Qian and
Sani R. Nassif and
Sachin S. Sapatnekar},
title = {Early-stage power grid analysis for uncertain working modes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {5},
pages = {676--682},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.846370},
doi = {10.1109/TCAD.2005.846370},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QianNS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghS05,
author = {Jaskirat Singh and
Sachin S. Sapatnekar},
title = {Congestion-aware topology optimization of structured power/ground
networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {5},
pages = {683--695},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.846369},
doi = {10.1109/TCAD.2005.846369},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShelarSSW05,
author = {Rupesh S. Shelar and
Sachin S. Sapatnekar and
Prashant Saxena and
Xinning Wang},
title = {A predictive distributed congestion metric with application to technology
mapping},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {5},
pages = {696--710},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.846368},
doi = {10.1109/TCAD.2005.846368},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShelarSSW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QianNS05a,
author = {Haifeng Qian and
Sani R. Nassif and
Sachin S. Sapatnekar},
title = {Power grid analysis using random walks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {8},
pages = {1204--1224},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.850863},
doi = {10.1109/TCAD.2005.850863},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QianNS05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangS05,
author = {Hongliang Chang and
Sachin S. Sapatnekar},
title = {Statistical timing analysis under spatial correlations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {9},
pages = {1467--1482},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.850834},
doi = {10.1109/TCAD.2005.850834},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShelarS05,
author = {Rupesh S. Shelar and
Sachin S. Sapatnekar},
title = {{BDD} decomposition for delay oriented pass transistor logic synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {957--970},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853601},
doi = {10.1109/TVLSI.2005.853601},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShelarS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KarandikarS05,
author = {Shrirang K. Karandikar and
Sachin S. Sapatnekar},
title = {Fast comparisons of circuit implementations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {12},
pages = {1329--1339},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.862727},
doi = {10.1109/TVLSI.2005.862727},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KarandikarS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SultaniaSS05,
author = {Anup Kumar Sultania and
Dennis Sylvester and
Sachin S. Sapatnekar},
title = {Gate oxide leakage and delay tradeoffs for dual-T\({}_{\mbox{ox}}\)
circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {12},
pages = {1362--1375},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.862723},
doi = {10.1109/TVLSI.2005.862723},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SultaniaSS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhangS05,
author = {Tianpei Zhang and
Sachin S. Sapatnekar},
editor = {Tingao Tang},
title = {Buffering global interconnects in structured {ASIC} design},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {23--26},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120735},
doi = {10.1145/1120725.1120735},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ZhangS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhanS05,
author = {Yong Zhan and
Sachin S. Sapatnekar},
editor = {Tingao Tang},
title = {Fast computation of the temperature distribution in {VLSI} chips using
the discrete cosine transform and table look-up},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {87--92},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120753},
doi = {10.1145/1120725.1120753},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ZhanS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SinghNLS05,
author = {Jaskirat Singh and
Vidyasagar Nookala and
Zhi{-}Quan Luo and
Sachin S. Sapatnekar},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Robust gate sizing by geometric programming},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {315--320},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065662},
doi = {10.1145/1065579.1065662},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SinghNLS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GoplenSS05,
author = {Brent Goplen and
Prashant Saxena and
Sachin S. Sapatnekar},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Net weighting to reduce repeater counts during placement},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {503--508},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065710},
doi = {10.1145/1065579.1065710},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/GoplenSS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChangS05,
author = {Hongliang Chang and
Sachin S. Sapatnekar},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Full-chip analysis of leakage power under process variations, including
spatial correlations},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {523--528},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065716},
doi = {10.1145/1065579.1065716},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChangS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/NookalaCLS05,
author = {Vidyasagar Nookala and
Ying Chen and
David J. Lilja and
Sachin S. Sapatnekar},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Microarchitecture-aware floorplanning using a statistical design of
experiments approach},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {579--584},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065731},
doi = {10.1145/1065579.1065731},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/NookalaCLS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MarquesRSR05,
author = {Felipe S. Marques and
Renato P. Ribas and
Sachin S. Sapatnekar and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {A new approach to the use of satisfiability in false path detection},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {308--311},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057735},
doi = {10.1145/1057661.1057735},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MarquesRSR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhanS05,
author = {Yong Zhan and
Sachin S. Sapatnekar},
title = {A high efficiency full-chip thermal simulation algorithm},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {635--638},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560144},
doi = {10.1109/ICCAD.2005.1560144},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhanS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/QianS05,
author = {Haifeng Qian and
Sachin S. Sapatnekar},
title = {A hybrid linear equation solver and its application in quadratic placement},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {905--909},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560190},
doi = {10.1109/ICCAD.2005.1560190},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/QianS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/SchneiderRSR05,
author = {Felipe Ribeiro Schneider and
Renato P. Ribas and
Sachin S. Sapatnekar and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {Exact lower bound for the number of switches in series to implement
a combinational logic cell},
booktitle = {23rd International Conference on Computer Design {(ICCD} 2005), 2-5
October 2005, San Jose, CA, {USA}},
pages = {357--362},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCD.2005.51},
doi = {10.1109/ICCD.2005.51},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/SchneiderRSR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/NookalaS05,
author = {Vidyasagar Nookala and
Sachin S. Sapatnekar},
title = {Designing optimized pipelined global interconnects: algorithms and
methodology impact},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {608--611},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464661},
doi = {10.1109/ISCAS.2005.1464661},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/NookalaS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KarandikarS05,
author = {Shrirang K. Karandikar and
Sachin S. Sapatnekar},
title = {Fast estimation of area-delay trade-offs in circuit sizing},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {3575--3578},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465402},
doi = {10.1109/ISCAS.2005.1465402},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/KarandikarS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/SinghS05,
author = {Jaskirat Singh and
Sachin S. Sapatnekar},
editor = {Patrick Groeneveld and
Louis Scheffer},
title = {A fast algorithm for power grid design},
booktitle = {Proceedings of the 2005 International Symposium on Physical Design,
{ISPD} 2005, San Francisco, California, USA, April 3-6, 2005},
pages = {70--77},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1055137.1055153},
doi = {10.1145/1055137.1055153},
timestamp = {Tue, 06 Nov 2018 11:07:46 +0100},
biburl = {https://dblp.org/rec/conf/ispd/SinghS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/ShelarSWS05,
author = {Rupesh S. Shelar and
Prashant Saxena and
Xinning Wang and
Sachin S. Sapatnekar},
editor = {Patrick Groeneveld and
Louis Scheffer},
title = {An efficient technology mapping algorithm targeting routing congestion
under delay constraints},
booktitle = {Proceedings of the 2005 International Symposium on Physical Design,
{ISPD} 2005, San Francisco, California, USA, April 3-6, 2005},
pages = {137--144},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1055137.1055166},
doi = {10.1145/1055137.1055166},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/ShelarSWS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/GoplenS05,
author = {Brent Goplen and
Sachin S. Sapatnekar},
editor = {Patrick Groeneveld and
Louis Scheffer},
title = {Thermal via placement in 3D ICs},
booktitle = {Proceedings of the 2005 International Symposium on Physical Design,
{ISPD} 2005, San Francisco, California, USA, April 3-6, 2005},
pages = {167--174},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1055137.1055171},
doi = {10.1145/1055137.1055171},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/GoplenS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SapatnekarRH05,
author = {Sachin S. Sapatnekar and
Jaijeet S. Roychowdhury and
Ramesh Harjani},
title = {High-Speed Interconnect Technology: On-Chip and Off-Chip},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {7},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.105},
doi = {10.1109/ICVD.2005.105},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SapatnekarRH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0010868,
author = {Sachin S. Sapatnekar},
title = {Timing},
publisher = {Kluwer},
year = {2004},
isbn = {978-1-4020-7671-8},
timestamp = {Thu, 07 Apr 2011 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0010868.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuHSN04,
author = {Haihua Su and
Jiang Hu and
Sachin S. Sapatnekar and
Sani R. Nassif},
title = {A methodology for the simultaneous design of supply and signal networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {12},
pages = {1614--1624},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2004.837728},
doi = {10.1109/TCAD.2004.837728},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuHSN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SundararajanSP04,
author = {Vijay Sundararajan and
Sachin S. Sapatnekar and
Keshab K. Parhi},
title = {A new approach for integration of min-area retiming and min-delay
padding for simultaneously addressing short-path and long-path constraints},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {9},
number = {3},
pages = {273--289},
year = {2004},
url = {https://doi.org/10.1145/1013948.1013949},
doi = {10.1145/1013948.1013949},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/SundararajanSP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/QianS04,
author = {Haifeng Qian and
Sachin S. Sapatnekar},
editor = {Masaharu Imai},
title = {Hierarchical random-walk algorithms for power grid analysis},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {499--504},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.109},
doi = {10.1109/ASPDAC.2004.109},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/QianS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ZhanHS04,
author = {Yong Zhan and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {On the selection of on-chip inductors for the optimal {VCO} design},
booktitle = {Proceedings of the {IEEE} 2004 Custom Integrated Circuits Conference,
{CICC} 2004, Orlando, FL, USA, October 2004},
pages = {277--280},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/CICC.2004.1358797},
doi = {10.1109/CICC.2004.1358797},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ZhanHS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/NookalaS04,
author = {Vidyasagar Nookala and
Sachin S. Sapatnekar},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {A method for correcting the functionality of a wire-pipelined circuit},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {570--575},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996724},
doi = {10.1145/996566.996724},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/NookalaS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SultaniaSS04,
author = {Anup Kumar Sultania and
Dennis Sylvester and
Sachin S. Sapatnekar},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {Tradeoffs between date oxide leakage and delay for dual T\({}_{\mbox{ox}}\)
circuits},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {761--766},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996773},
doi = {10.1145/996566.996773},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SultaniaSS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ZhanS04,
author = {Yong Zhan and
Sachin S. Sapatnekar},
title = {Optimization of Integrated Spiral Inductors Using Sequential Quadratic
Programming},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {622--629},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1268914},
doi = {10.1109/DATE.2004.1268914},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ZhanS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KarandikarS04,
author = {Shrirang K. Karandikar and
Sachin S. Sapatnekar},
title = {Fast Comparisons of Circuit Implementations},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {910--915},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1269005},
doi = {10.1109/DATE.2004.1269005},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KarandikarS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/QianKNS04,
author = {Haifeng Qian and
Joseph N. Kozhaya and
Sani R. Nassif and
Sachin S. Sapatnekar},
title = {A chip-level electrostatic discharge simulation strategy},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {315--318},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382593},
doi = {10.1109/ICCAD.2004.1382593},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/QianKNS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KarandikarS04,
author = {Shrirang K. Karandikar and
Sachin S. Sapatnekar},
title = {Logical effort based technology mapping},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {419--422},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382611},
doi = {10.1109/ICCAD.2004.1382611},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KarandikarS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/AlpertHSS04,
author = {Charles J. Alpert and
Jiang Hu and
Sachin S. Sapatnekar and
Cliff C. N. Sze},
title = {Accurate estimation of global buffer delay within a floorplan},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {706--711},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382667},
doi = {10.1109/ICCAD.2004.1382667},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/AlpertHSS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ZhangS04,
author = {Tianpei Zhang and
Sachin S. Sapatnekar},
title = {Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction
in Global Routing},
booktitle = {22nd {IEEE} International Conference on Computer Design: {VLSI} in
Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San
Jose, CA, USA, Proceedings},
pages = {93--98},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICCD.2004.1347906},
doi = {10.1109/ICCD.2004.1347906},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ZhangS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/SultaniaSS04,
author = {Anup Kumar Sultania and
Dennis Sylvester and
Sachin S. Sapatnekar},
title = {Transistor and Pin Reordering for Gate Oxide Leakage Reduction in
Dual T\{ox\} Circuits},
booktitle = {22nd {IEEE} International Conference on Computer Design: {VLSI} in
Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San
Jose, CA, USA, Proceedings},
pages = {228--233},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICCD.2004.1347927},
doi = {10.1109/ICCD.2004.1347927},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/SultaniaSS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/SinghS04,
author = {Jaskirat Singh and
Sachin S. Sapatnekar},
editor = {Charles J. Alpert and
Patrick Groeneveld},
title = {Topology optimization of structured power/ground networks},
booktitle = {Proceedings of the 2004 International Symposium on Physical Design,
{ISPD} 2004, Phoenix, Arizona, USA, April 18-21, 2004},
pages = {116--123},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/981066.981093},
doi = {10.1145/981066.981093},
timestamp = {Tue, 06 Nov 2018 11:07:46 +0100},
biburl = {https://dblp.org/rec/conf/ispd/SinghS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/QianNS04,
author = {Haifeng Qian and
Sani R. Nassif and
Sachin S. Sapatnekar},
editor = {Charles J. Alpert and
Patrick Groeneveld},
title = {Early-stage power grid analysis for uncertain working modes},
booktitle = {Proceedings of the 2004 International Symposium on Physical Design,
{ISPD} 2004, Phoenix, Arizona, USA, April 18-21, 2004},
pages = {132--137},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/981066.981095},
doi = {10.1145/981066.981095},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispd/QianNS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/ShelarSSW04,
author = {Rupesh S. Shelar and
Sachin S. Sapatnekar and
Prashant Saxena and
Xinning Wang},
editor = {Charles J. Alpert and
Patrick Groeneveld},
title = {A predictive distributed congestion metric and its application to
technology mapping},
booktitle = {Proceedings of the 2004 International Symposium on Physical Design,
{ISPD} 2004, Phoenix, Arizona, USA, April 18-21, 2004},
pages = {210--217},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/981066.981111},
doi = {10.1145/981066.981111},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/ShelarSSW04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ChangQS04,
author = {Hongliang Chang and
Haifeng Qian and
Sachin S. Sapatnekar},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {The Certainty of Uncertainty: Randomness in Nanometer Design},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {36--47},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_6},
doi = {10.1007/978-3-540-30205-6\_6},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ChangQS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/Sapatnekar04,
author = {Sachin S. Sapatnekar},
title = {High-Performance Power Grids For Nanometer Technologies},
booktitle = {17th International Conference on {VLSI} Design {(VLSI} Design 2004),
with the 3rd International Conference on Embedded Systems Design,
5-9 January 2004, Mumbai, India},
pages = {839--844},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICVD.2004.1261036},
doi = {10.1109/ICVD.2004.1261036},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/Sapatnekar04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/SapatnekarS03,
author = {Sachin S. Sapatnekar and
Haihua Su},
title = {Analysis and Optimization of Power Grids},
journal = {{IEEE} Des. Test Comput.},
volume = {20},
number = {3},
pages = {7--15},
year = {2003},
url = {https://doi.org/10.1109/MDT.2003.1198680},
doi = {10.1109/MDT.2003.1198680},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/SapatnekarS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuBZGZPS03,
author = {Haitian Hu and
David T. Blaauw and
Vladimir Zolotov and
Kaushik Gala and
Min Zhao and
Rajendran Panda and
Sachin S. Sapatnekar},
title = {Fast on-chip inductance simulation using a precorrected-FFT method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {1},
pages = {49--66},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2002.805719},
doi = {10.1109/TCAD.2002.805719},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuBZGZPS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertS03,
author = {Charles J. Alpert and
Sachin S. Sapatnekar},
title = {Guest editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {4},
pages = {385--386},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.809644},
doi = {10.1109/TCAD.2003.809644},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuSN03,
author = {Haihua Su and
Sachin S. Sapatnekar and
Sani R. Nassif},
title = {Optimal decoupling capacitor sizing and placement for standard-cell
layout designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {4},
pages = {428--436},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.809658},
doi = {10.1109/TCAD.2003.809658},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuSN03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertHSV03,
author = {Charles J. Alpert and
Jiang Hu and
Sachin S. Sapatnekar and
Paul Villarrubia},
title = {A practical methodology for early buffer and wire resource allocation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {5},
pages = {573--583},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.810749},
doi = {10.1109/TCAD.2003.810749},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertHSV03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuGS03,
author = {Haihua Su and
Kaushik Gala and
Sachin S. Sapatnekar},
title = {Analysis and optimization of structured power/ground networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {11},
pages = {1533--1544},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.818372},
doi = {10.1109/TCAD.2003.818372},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuGS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KarandikarS03,
author = {Shrirang K. Karandikar and
Sachin S. Sapatnekar},
title = {Technology mapping for {SOI} domino logic incorporating solutions
for the parasitic bipolar effect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1094--1105},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817137},
doi = {10.1109/TVLSI.2003.817137},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KarandikarS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/QianNS03,
author = {Haifeng Qian and
Sani R. Nassif and
Sachin S. Sapatnekar},
title = {Random walks in a supply network},
booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
Anaheim, CA, USA, June 2-6, 2003},
pages = {93--98},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/775832.775860},
doi = {10.1145/775832.775860},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/QianNS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/GoplenS03,
author = {Brent Goplen and
Sachin S. Sapatnekar},
title = {Efficient Thermal Placement of Standard Cells in 3D ICs using a Force
Directed Approach},
booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003,
San Jose, CA, USA, November 9-13, 2003},
pages = {86--90},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2003},
url = {https://doi.org/10.1109/ICCAD.2003.1257591},
doi = {10.1109/ICCAD.2003.1257591},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/GoplenS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChangS03,
author = {Hongliang Chang and
Sachin S. Sapatnekar},
title = {Statistical Timing Analysis Considering Spatial Correlations using
a Single Pert-Like Traversal},
booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003,
San Jose, CA, USA, November 9-13, 2003},
pages = {621--626},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257875},
doi = {10.1109/ICCAD.2003.1257875},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChangS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/RajappanS03,
author = {Venkatesan Rajappan and
Sachin S. Sapatnekar},
title = {An Efficient Algorithm for Calculating the Worst-case Delay due to
Crosstalk},
booktitle = {21st International Conference on Computer Design {(ICCD} 2003),VLSI
in Computers and Processors, 13-15 October 2003, San Jose, CA, USA,
Proceedings},
pages = {76},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICCD.2003.1240876},
doi = {10.1109/ICCD.2003.1240876},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/RajappanS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HuBZGZPS03,
author = {Haitian Hu and
David T. Blaauw and
Vladimir Zolotov and
Kaushik Gala and
Min Zhao and
Rajendran Panda and
Sachin S. Sapatnekar},
title = {Table look-up based compact modeling for on-chip interconnect timing
and noise analysis},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {668--671},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206190},
doi = {10.1109/ISCAS.2003.1206190},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HuBZGZPS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/ChenS03,
author = {Guoqiang Chen and
Sachin S. Sapatnekar},
editor = {Massoud Pedram and
Charles J. Alpert},
title = {Partition-driven standard cell thermal placement},
booktitle = {Proceedings of the 2003 International Symposium on Physical Design,
{ISPD} 2003, Monterey, CA, USA, April 6-9, 2003},
pages = {75--80},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/640000.640018},
doi = {10.1145/640000.640018},
timestamp = {Tue, 06 Nov 2018 11:07:46 +0100},
biburl = {https://dblp.org/rec/conf/ispd/ChenS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RamanSA02,
author = {Suresh Raman and
Sachin S. Sapatnekar and
Charles J. Alpert},
title = {Probability-driven routing in a datapath environment},
journal = {Integr.},
volume = {31},
number = {2},
pages = {159--182},
year = {2002},
url = {https://doi.org/10.1016/S0167-9260(02)00024-X},
doi = {10.1016/S0167-9260(02)00024-X},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RamanSA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoPSB02,
author = {Min Zhao and
Rajendran Panda and
Sachin S. Sapatnekar and
David T. Blaauw},
title = {Hierarchical analysis of power distribution networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {159--168},
year = {2002},
url = {https://doi.org/10.1109/43.980256},
doi = {10.1109/43.980256},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoPSB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SundararajanSP02,
author = {Vijay Sundararajan and
Sachin S. Sapatnekar and
Keshab K. Parhi},
title = {Fast and exact transistor sizing based on iterative relaxation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {568--581},
year = {2002},
url = {https://doi.org/10.1109/43.998628},
doi = {10.1109/43.998628},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SundararajanSP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuS02,
author = {Jiang Hu and
Sachin S. Sapatnekar},
title = {A timing-constrained simultaneous global routing algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1025--1036},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801083},
doi = {10.1109/TCAD.2002.801083},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ZhaoS02,
author = {Min Zhao and
Sachin S. Sapatnekar},
title = {Technology mapping algorithms for domino logic},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {7},
number = {2},
pages = {306--335},
year = {2002},
url = {https://doi.org/10.1145/544536.544541},
doi = {10.1145/544536.544541},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ZhaoS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PangjunS02,
author = {Jatuchai Pangjun and
Sachin S. Sapatnekar},
title = {Low-power clock distribution using multiple voltages and reduced swings},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {309--318},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043334},
doi = {10.1109/TVLSI.2002.1043334},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PangjunS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuS02,
author = {Haitian Hu and
Sachin S. Sapatnekar},
title = {Efficient inductance extraction using circuit-aware techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {746--761},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808455},
doi = {10.1109/TVLSI.2002.808455},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/HuS02,
author = {Jiang Hu and
Sachin S. Sapatnekar},
title = {Performance Driven Global Routing Through Gradual Refinement},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {595--604},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012219},
doi = {10.1080/1065514021000012219},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/HuS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SuHSN02,
author = {Haihua Su and
Jiang Hu and
Sachin S. Sapatnekar and
Sani R. Nassif},
title = {Congestion-driven codesign of power and signal networks},
booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002,
New Orleans, LA, USA, June 10-14, 2002},
pages = {64--69},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/513918.513936},
doi = {10.1145/513918.513936},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SuHSN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HuBZGZPS02,
author = {Haitian Hu and
David T. Blaauw and
Vladimir Zolotov and
Kaushik Gala and
Min Zhao and
Rajendran Panda and
Sachin S. Sapatnekar},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {A precorrected-FFT method for simulating on-chip inductance},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {221--227},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774605},
doi = {10.1145/774572.774605},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HuBZGZPS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KetkarS02,
author = {Mahesh Ketkar and
Sachin S. Sapatnekar},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {Standby power optimization via transistor sizing and dual threshold
voltage assignment},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {375--378},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774628},
doi = {10.1145/774572.774628},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KetkarS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/HuS02,
author = {Haitian Hu and
Sachin S. Sapatnekar},
title = {Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques},
booktitle = {20th International Conference on Computer Design {(ICCD} 2002), {VLSI}
in Computers and Processors, 16-18 September 2002, Freiburg, Germany,
Proceedings},
pages = {434},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ICCD.2002.1106808},
doi = {10.1109/ICCD.2002.1106808},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/HuS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/SuSN02,
author = {Haihua Su and
Sachin S. Sapatnekar and
Sani R. Nassif},
editor = {Sachin S. Sapatnekar and
Massoud Pedram},
title = {An algorithm for optimal decoupling capacitor sizing and placement
for standard cell layouts},
booktitle = {Proceedings of 2002 International Symposium on Physical Design, {ISPD}
2002, Del Mar, CA, USA, April 7-10, 2002},
pages = {68--73},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505388.505405},
doi = {10.1145/505388.505405},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/SuSN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/ShelarS02,
author = {Rupesh S. Shelar and
Sachin S. Sapatnekar},
title = {Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {209--214},
year = {2002},
timestamp = {Sun, 04 Aug 2019 18:01:44 +0200},
biburl = {https://dblp.org/rec/conf/iwls/ShelarS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhangS02,
author = {Tianpei Zhang and
Sachin S. Sapatnekar},
title = {Optimized pin assignment for lower routing congestion after floorplanning
phase},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {17--21},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505352},
doi = {10.1145/505348.505352},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ZhangS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ShelarS02,
author = {Rupesh S. Shelar and
Sachin S. Sapatnekar},
title = {An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis},
booktitle = {Proceedings of the 7th Asia and South Pacific Design Automation Conference
{(ASP-DAC} 2002), and the 15th International Conference on {VLSI}
Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002},
pages = {87--92},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ASPDAC.2002.994890},
doi = {10.1109/ASPDAC.2002.994890},
timestamp = {Mon, 14 Nov 2022 15:28:09 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ShelarS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ispd/2002,
editor = {Sachin S. Sapatnekar and
Massoud Pedram},
title = {Proceedings of 2002 International Symposium on Physical Design, {ISPD}
2002, Del Mar, CA, USA, April 7-10, 2002},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505388},
doi = {10.1145/505388},
isbn = {1-58113-460-6},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/2002.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HuS01,
author = {Jiang Hu and
Sachin S. Sapatnekar},
title = {A survey on multi-net global routing for integrated circuits},
journal = {Integr.},
volume = {31},
number = {1},
pages = {1--49},
year = {2001},
url = {https://doi.org/10.1016/S0167-9260(01)00020-7},
doi = {10.1016/S0167-9260(01)00020-7},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HuS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertGHNQS01,
author = {Charles J. Alpert and
Gopal Gandham and
Jiang Hu and
Jos{\'{e}} Luis Neves and
Stephen T. Quay and
Sachin S. Sapatnekar},
title = {Steiner tree optimization for buffers, blockages, and bays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {4},
pages = {556--562},
year = {2001},
url = {https://doi.org/10.1109/43.918213},
doi = {10.1109/43.918213},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertGHNQS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuhlmannS01,
author = {Martin Kuhlmann and
Sachin S. Sapatnekar},
title = {Exact and efficient crosstalk estimation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {7},
pages = {858--866},
year = {2001},
url = {https://doi.org/10.1109/43.931008},
doi = {10.1109/43.931008},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuhlmannS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiangSB01,
author = {Yanbin Jiang and
Sachin S. Sapatnekar and
Cyrus Bamji},
title = {Technology mapping for high-performance static {CMOS} and pass transistor
logic designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {9},
number = {5},
pages = {577--589},
year = {2001},
url = {https://doi.org/10.1109/92.953492},
doi = {10.1109/92.953492},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiangSB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/HuS01,
author = {Haitian Hu and
Sachin S. Sapatnekar},
title = {Circuit-aware on-chip inductance extraction},
booktitle = {Proceedings of the {IEEE} 2001 Custom Integrated Circuits Conference,
{CICC} 2001, San Diego, CA, USA, May 6-9, 2001},
pages = {245--248},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/CICC.2001.929765},
doi = {10.1109/CICC.2001.929765},
timestamp = {Mon, 10 Oct 2022 09:13:22 +0200},
biburl = {https://dblp.org/rec/conf/cicc/HuS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AlpertHSV01,
author = {Charles J. Alpert and
Jiang Hu and
Sachin S. Sapatnekar and
Paul Villarrubia},
title = {A Practical Methodology for Early Buffer and Wire Resource Allocation},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {189--194},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.378461},
doi = {10.1145/378239.378461},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/AlpertHSV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhaoS01,
author = {Min Zhao and
Sachin S. Sapatnekar},
title = {A New Structural Pattern Matching Algorithm for Technology Mapping},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {371--376},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.378526},
doi = {10.1145/378239.378526},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ZhaoS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KarandikarS01,
author = {Shrirang K. Karandikar and
Sachin S. Sapatnekar},
title = {Technology Mapping for {SOI} Domino Logic Incorporating Solutions
for the Parasitic Bipolar Effect},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {377--382},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.378527},
doi = {10.1145/378239.378527},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KarandikarS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SuS01,
author = {Haihua Su and
Sachin S. Sapatnekar},
editor = {Rolf Ernst},
title = {Hybrid Structured Clock Network Construction},
booktitle = {Proceedings of the 2001 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2001, San Jose, CA, USA, November 4-8, 2001},
pages = {333--336},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCAD.2001.968643},
doi = {10.1109/ICCAD.2001.968643},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SuS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ShelarS01,
author = {Rupesh S. Shelar and
Sachin S. Sapatnekar},
editor = {Rolf Ernst},
title = {Recursive Bipartitioning of BDDs for Performance Driven Synthesis
of Pass Transistor Logic Circuits},
booktitle = {Proceedings of the 2001 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2001, San Jose, CA, USA, November 4-8, 2001},
pages = {449--452},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCAD.2001.968674},
doi = {10.1109/ICCAD.2001.968674},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ShelarS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/HuS01,
author = {Jiang Hu and
Sachin S. Sapatnekar},
title = {Performance Driven Global Routing Through Gradual Refinement},
booktitle = {19th International Conference on Computer Design {(ICCD} 2001), {VLSI}
in Computers and Processors, 23-26 September 2001, Austin, TX, USA,
Proceedings},
pages = {481--483},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCD.2001.955070},
doi = {10.1109/ICCD.2001.955070},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/HuS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AlpertGHNQS01,
author = {Charles J. Alpert and
Gopal Gandham and
Jiang Hu and
Jos{\'{e}} Luis Neves and
Stephen T. Quay and
Sachin S. Sapatnekar},
title = {Steiner tree optimization for buffers. Blockages and bays},
booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems,
{ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
pages = {399--402},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ISCAS.2001.922069},
doi = {10.1109/ISCAS.2001.922069},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AlpertGHNQS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/AlpertHHKLLQSSV01,
author = {Charles J. Alpert and
Milos Hrkic and
Jiang Hu and
Andrew B. Kahng and
John Lillis and
Bao Liu and
Stephen T. Quay and
Sachin S. Sapatnekar and
A. J. Sullivan and
Paul Villarrubia},
editor = {Sachin S. Sapatnekar and
Manfred Wiesel},
title = {Buffered Steiner trees for difficult instances},
booktitle = {Proceedings of the 2001 International Symposium on Physical Design,
{ISPD} 2001, Sonoma County, CA, USA, April 1-4, 2001},
pages = {4--9},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/369691.369699},
doi = {10.1145/369691.369699},
timestamp = {Thu, 21 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/AlpertHHKLLQSSV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/MenezesS01,
author = {Noel Menezes and
Sachin S. Sapatnekar},
title = {Optimization and Analysis Techniques for the Deep Submicron Regime},
booktitle = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
3-7 January 2001, Bangalore, India},
pages = {3--4},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2001.10019},
doi = {10.1109/VLSID.2001.10019},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/MenezesS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ispd/2001,
editor = {Sachin S. Sapatnekar and
Manfred Wiesel},
title = {Proceedings of the 2001 International Symposium on Physical Design,
{ISPD} 2001, Sonoma County, CA, USA, April 1-4, 2001},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/369691},
doi = {10.1145/369691},
isbn = {1-58113-347-2},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/2001.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuS00,
author = {Jiang Hu and
Sachin S. Sapatnekar},
title = {Algorithms for non-Hanan-based optimization for {VLSI} interconnectunder
a higher-order {AWE} model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {19},
number = {4},
pages = {446--458},
year = {2000},
url = {https://doi.org/10.1109/43.838994},
doi = {10.1109/43.838994},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sapatnekar00,
author = {Sachin S. Sapatnekar},
title = {A timing model incorporating the effect of crosstalk on delay andits
application to optimal channel routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {19},
number = {5},
pages = {550--559},
year = {2000},
url = {https://doi.org/10.1109/43.845079},
doi = {10.1109/43.845079},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sapatnekar00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KasamsettyKS00,
author = {Kishore Kasamsetty and
Mahesh Ketkar and
Sachin S. Sapatnekar},
title = {A new class of convex functions for delay modeling and itsapplication
to the transistor sizing problem {[CMOS} gates]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {19},
number = {7},
pages = {779--788},
year = {2000},
url = {https://doi.org/10.1109/43.851993},
doi = {10.1109/43.851993},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KasamsettyKS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoS00,
author = {Min Zhao and
Sachin S. Sapatnekar},
title = {Timing-driven partitioning and timing optimization of mixedstatic-domino
implementations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {19},
number = {11},
pages = {1322--1336},
year = {2000},
url = {https://doi.org/10.1109/43.892856},
doi = {10.1109/43.892856},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SapatnekarC00,
author = {Sachin S. Sapatnekar and
Weitong Chuang},
title = {Power-delay optimizations in gate sizing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {1},
pages = {98--114},
year = {2000},
url = {https://doi.org/10.1145/329458.329473},
doi = {10.1145/329458.329473},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/SapatnekarC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhaoPSECB00,
author = {Min Zhao and
Rajendran Panda and
Sachin S. Sapatnekar and
Tim Edwards and
Rajat Chaudhry and
David T. Blaauw},
editor = {Giovanni De Micheli},
title = {Hierarchical analysis of power distribution networks},
booktitle = {Proceedings of the 37th Conference on Design Automation, Los Angeles,
CA, USA, June 5-9, 2000},
pages = {150--155},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/337292.337355},
doi = {10.1145/337292.337355},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ZhaoPSECB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SundararajanSP00,
author = {Vijay Sundararajan and
Sachin S. Sapatnekar and
Keshab K. Parhi},
editor = {Giovanni De Micheli},
title = {{MINFLOTRANSIT:} min-cost flow based transistor sizing tool},
booktitle = {Proceedings of the 37th Conference on Design Automation, Los Angeles,
CA, USA, June 5-9, 2000},
pages = {649--664},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/337292.337606},
doi = {10.1145/337292.337606},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SundararajanSP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KetkarKS00,
author = {Mahesh Ketkar and
Kishore Kasamsetty and
Sachin S. Sapatnekar},
editor = {Giovanni De Micheli},
title = {Convex delay models for transistor sizing},
booktitle = {Proceedings of the 37th Conference on Design Automation, Los Angeles,
CA, USA, June 5-9, 2000},
pages = {655--660},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/337292.337607},
doi = {10.1145/337292.337607},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KetkarKS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HuS00,
author = {Jiang Hu and
Sachin S. Sapatnekar},
editor = {Ellen Sentovich},
title = {A Timing-Constrained Algorithm for Simultaneous Global Routing of
Multiple Nets},
booktitle = {Proceedings of the 2000 {IEEE/ACM} International Conference on Computer-Aided
Design, 2000, San Jose, California, USA, November 5-9, 2000},
pages = {99--103},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCAD.2000.896457},
doi = {10.1109/ICCAD.2000.896457},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HuS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SuGS00,
author = {Haihua Su and
Kaushik Gala and
Sachin S. Sapatnekar},
editor = {Ellen Sentovich},
title = {Fast Analysis and Optimization of Power/Ground Networks},
booktitle = {Proceedings of the 2000 {IEEE/ACM} International Conference on Computer-Aided
Design, 2000, San Jose, California, USA, November 5-9, 2000},
pages = {477--480},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCAD.2000.896518},
doi = {10.1109/ICCAD.2000.896518},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SuGS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhaoS00,
author = {Min Zhao and
Sachin S. Sapatnekar},
title = {Dual-monotonic domino gate mapping and optimal output phase assignment
of domino logic},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {309--312},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.856323},
doi = {10.1109/ISCAS.2000.856323},
timestamp = {Fri, 13 Aug 2021 09:26:01 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ZhaoS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/RamanSA00,
author = {Suresh Raman and
Sachin S. Sapatnekar and
Charles J. Alpert},
editor = {Manfred Wiesel and
Dwight D. Hill},
title = {Datapath routing based on a decongestion metric},
booktitle = {Proceedings of the 2000 International Symposium on Physical Design,
{ISPD} 2000, San Diego, CA, USA, April 9-12, 2000},
pages = {122--127},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/332357.332387},
doi = {10.1145/332357.332387},
timestamp = {Thu, 26 Aug 2021 17:11:38 +0200},
biburl = {https://dblp.org/rec/conf/ispd/RamanSA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/Sapatnekar00,
author = {Sachin S. Sapatnekar},
title = {Capturing the Effect of Crosstalk on Delay},
booktitle = {13th International Conference on {VLSI} Design {(VLSI} Design 2000),
4-7 January 2000, Calcutta, India},
pages = {364--369},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICVD.2000.812634},
doi = {10.1109/ICVD.2000.812634},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/Sapatnekar00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaheshwariS99,
author = {Naresh Maheshwari and
Sachin S. Sapatnekar},
title = {Retiming control logic},
journal = {Integr.},
volume = {28},
number = {1},
pages = {33--53},
year = {1999},
url = {https://doi.org/10.1016/S0167-9260(99)00010-3},
doi = {10.1016/S0167-9260(99)00010-3},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MaheshwariS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HouHS99,
author = {Huibo Hou and
Jiang Hu and
Sachin S. Sapatnekar},
title = {Non-Hanan routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {436--444},
year = {1999},
url = {https://doi.org/10.1109/43.752927},
doi = {10.1109/43.752927},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HouHS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaheshwariS99,
author = {Naresh Maheshwari and
Sachin S. Sapatnekar},
title = {Optimizing large multiphase level-clocked circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1249--1264},
year = {1999},
url = {https://doi.org/10.1109/43.784118},
doi = {10.1109/43.784118},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaheshwariS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HuS99,
author = {Jiang Hu and
Sachin S. Sapatnekar},
editor = {Mary Jane Irwin},
title = {{FAR-DS:} Full-Plane {AWE} Routing with Driver Sizing},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {84--89},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.309881},
doi = {10.1145/309847.309881},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/HuS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SundararajanSP99,
author = {Vijay Sundararajan and
Sachin S. Sapatnekar and
Keshab K. Parhi},
editor = {Jacob K. White and
Ellen Sentovich},
title = {Marsh: min-area retiming with setup and hold constraints},
booktitle = {Proceedings of the 1999 {IEEE/ACM} International Conference on Computer-Aided
Design, 1999, San Jose, California, USA, November 7-11, 1999},
pages = {2--6},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCAD.1999.810609},
doi = {10.1109/ICCAD.1999.810609},
timestamp = {Mon, 08 May 2023 21:43:38 +0200},
biburl = {https://dblp.org/rec/conf/iccad/SundararajanSP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/JiangS99,
author = {Yanbin Jiang and
Sachin S. Sapatnekar},
editor = {Jacob K. White and
Ellen Sentovich},
title = {An integrated algorithm for combined placement and libraryless technology
mapping},
booktitle = {Proceedings of the 1999 {IEEE/ACM} International Conference on Computer-Aided
Design, 1999, San Jose, California, USA, November 7-11, 1999},
pages = {102--106},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCAD.1999.810630},
doi = {10.1109/ICCAD.1999.810630},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/JiangS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhaoS99,
author = {Min Zhao and
Sachin S. Sapatnekar},
editor = {Jacob K. White and
Ellen Sentovich},
title = {Timing-driven partitioning for two-phase domino and mixed static/domino
implementations},
booktitle = {Proceedings of the 1999 {IEEE/ACM} International Conference on Computer-Aided
Design, 1999, San Jose, California, USA, November 7-11, 1999},
pages = {107--110},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCAD.1999.810631},
doi = {10.1109/ICCAD.1999.810631},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhaoS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/KuhlmannSP99,
author = {Martin Kuhlmann and
Sachin S. Sapatnekar and
Keshab K. Parhi},
title = {Efficient Crosstalk Estimation},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design,
{VLSI} in Computers and Processors, {ICCD} '99, Austin, Texas, USA,
October 10-13, 1999},
pages = {266},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCD.1999.808435},
doi = {10.1109/ICCD.1999.808435},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/KuhlmannSP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/PangjunS99,
author = {Jatuchai Pangjun and
Sachin S. Sapatnekar},
editor = {Farid N. Najm and
Jason Cong and
David T. Blaauw},
title = {Clock distribution using multiple voltages},
booktitle = {Proceedings of the 1999 International Symposium on Low Power Electronics
and Design, 1999, San Diego, California, USA, August 16-17, 1999},
pages = {145--150},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/313817.313902},
doi = {10.1145/313817.313902},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/PangjunS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/HuS99,
author = {Jiang Hu and
Sachin S. Sapatnekar},
editor = {D. F. Wong},
title = {Simultaneous buffer insertion and non-Hanan optimization for {VLSI}
interconnect under a higher order {AWE} model},
booktitle = {Proceedings of the 1999 International Symposium on Physical Design,
{ISPD} 1999, Monterey, CA, USA, April 12-14, 1999},
pages = {133--138},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/299996.300041},
doi = {10.1145/299996.300041},
timestamp = {Sun, 02 Oct 2022 16:10:02 +0200},
biburl = {https://dblp.org/rec/conf/ispd/HuS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SathyamurthySF98,
author = {Harsha Sathyamurthy and
Sachin S. Sapatnekar and
John P. Fishburn},
title = {Speeding up pipelined circuits through a combination of gate sizing
and clock skew optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {173--182},
year = {1998},
url = {https://doi.org/10.1109/43.681267},
doi = {10.1109/43.681267},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SathyamurthySF98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaheshwariS98,
author = {Naresh Maheshwari and
Sachin S. Sapatnekar},
title = {Efficient retiming of large circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {6},
number = {1},
pages = {74--83},
year = {1998},
url = {https://doi.org/10.1109/92.661250},
doi = {10.1109/92.661250},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaheshwariS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiangSBK98,
author = {Yanbin Jiang and
Sachin S. Sapatnekar and
Cyrus Bamji and
Juho Kim},
title = {Interleaving buffer insertion and transistor sizing into a single
optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {6},
number = {4},
pages = {625--633},
year = {1998},
url = {https://doi.org/10.1109/92.736136},
doi = {10.1109/92.736136},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiangSBK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/JiangSBK98,
author = {Yanbin Jiang and
Sachin S. Sapatnekar and
Cyrus Bamji and
Juho Kim},
title = {Combined transistor sizing with buffer insertion for timing optimization},
booktitle = {Proceedings of the {IEEE} 1998 Custom Integrated Circuits Conference,
{CICC} 1998, Santa Clara, CA, USA, May 11-14, 1998},
pages = {605--608},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/CICC.1998.695051},
doi = {10.1109/CICC.1998.695051},
timestamp = {Fri, 07 Jul 2023 11:00:51 +0200},
biburl = {https://dblp.org/rec/conf/cicc/JiangSBK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MaheshwariS98,
author = {Naresh Maheshwari and
Sachin S. Sapatnekar},
editor = {Patrick M. Dewilde and
Franz J. Rammig and
Gerry Musgrave},
title = {Efficient Minarea Retiming of Large Level-Clocked Circuits},
booktitle = {1998 Design, Automation and Test in Europe {(DATE} '98), February
23-26, 1998, Le Palais des Congr{\`{e}}s de Paris, Paris, France},
pages = {840--845},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/DATE.1998.655956},
doi = {10.1109/DATE.1998.655956},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/MaheshwariS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhaoS98,
author = {Min Zhao and
Sachin S. Sapatnekar},
editor = {Hiroto Yasuura},
title = {Technology mapping for domino logic},
booktitle = {Proceedings of the 1998 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1998, San Jose, CA, USA, November 8-12, 1998},
pages = {248--251},
publisher = {{ACM} / {IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1145/288548.288621},
doi = {10.1145/288548.288621},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhaoS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/JiangSB98,
author = {Yanbin Jiang and
Sachin S. Sapatnekar and
Cyrus Bamji},
title = {A fast global gate collapsing technique for high performance designs
using static {CMOS} and pass transistor logic},
booktitle = {International Conference on Computer Design: {VLSI} in Computers and
Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
{USA}},
pages = {276--281},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICCD.1998.727062},
doi = {10.1109/ICCD.1998.727062},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/JiangSB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/HouS98,
author = {Huibo Hou and
Sachin S. Sapatnekar},
editor = {Majid Sarrafzadeh},
title = {Routing tree topology construction to meet interconnect timing constraints},
booktitle = {Proceedings of the 1998 International Symposium on Physical Design,
{ISPD} 1998, Monterey, CA, USA, April 6-8, 1998},
pages = {205--210},
publisher = {{ACM}},
year = {1998},
url = {https://doi.org/10.1145/274535.274565},
doi = {10.1145/274535.274565},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/HouS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/RamaswamySB97,
author = {Shankar Ramaswamy and
Sachin S. Sapatnekar and
Prithviraj Banerjee},
title = {A Framework for Exploiting Task and Data Parallelism on Distributed
Memory Multicomputers},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {8},
number = {11},
pages = {1098--1116},
year = {1997},
url = {https://doi.org/10.1109/71.642945},
doi = {10.1109/71.642945},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/RamaswamySB97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MaheshwariS97,
author = {Naresh Maheshwari and
Sachin S. Sapatnekar},
editor = {Ellen J. Yoffa and
Giovanni De Micheli and
Jan M. Rabaey},
title = {An Improved Algorithm for Minimum-Area Retiming},
booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim,
California, USA, Anaheim Convention Center, June 9-13, 1997},
pages = {2--7},
publisher = {{ACM} Press},
year = {1997},
url = {https://doi.org/10.1145/266021.266025},
doi = {10.1145/266021.266025},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MaheshwariS97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MaheshwariS97,
author = {Naresh Maheshwari and
Sachin S. Sapatnekar},
editor = {Ralph H. J. M. Otten and
Hiroto Yasuura},
title = {Minimum area retiming with equivalent initial states},
booktitle = {Proceedings of the 1997 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1997, San Jose, CA, USA, November 9-13, 1997},
pages = {216--219},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1997},
url = {https://doi.org/10.1109/ICCAD.1997.643523},
doi = {10.1109/ICCAD.1997.643523},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MaheshwariS97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/KimBJS97,
author = {Juho Kim and
Cyrus Bamji and
Yanbin Jiang and
Sachin S. Sapatnekar},
editor = {Andrew B. Kahng and
Majid Sarrafzadeh},
title = {Concurrent transistor sizing and buffer insertion by considering cost-delay
tradeoffs},
booktitle = {Proceedings of the 1997 International Symposium on Physical Design,
{ISPD} 1997, Napa Valley, California, USA, April 14-16, 1997},
pages = {130--135},
publisher = {{ACM}},
year = {1997},
url = {https://doi.org/10.1145/267665.267703},
doi = {10.1145/267665.267703},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/KimBJS97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sapatnekar96,
author = {Sachin S. Sapatnekar},
title = {Wire sizing as a convex optimization problem: exploring the area-delay
tradeoff},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {15},
number = {8},
pages = {1001--1011},
year = {1996},
url = {https://doi.org/10.1109/43.511579},
doi = {10.1109/43.511579},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sapatnekar96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SanchetiS96,
author = {Piyush K. Sancheti and
Sachin S. Sapatnekar},
title = {Optimal design of macrocells for low power and high speed},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {15},
number = {9},
pages = {1160--1166},
year = {1996},
url = {https://doi.org/10.1109/43.536722},
doi = {10.1109/43.536722},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SanchetiS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SapatnekarD96,
author = {Sachin S. Sapatnekar and
Rahul B. Deokar},
title = {Utilizing the retiming-skew equivalence in a practical algorithm for
retiming large circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {15},
number = {10},
pages = {1237--1248},
year = {1996},
url = {https://doi.org/10.1109/43.541443},
doi = {10.1109/43.541443},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SapatnekarD96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LehtherS96,
author = {Daksh Lehther and
Sachin S. Sapatnekar},
editor = {Rob A. Rutenbar and
Ralph H. J. M. Otten},
title = {Clock tree synthesis for multi-chip modules},
booktitle = {Proceedings of the 1996 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1996, San Jose, CA, USA, November 10-14, 1996},
pages = {50--53},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1996},
url = {https://doi.org/10.1109/ICCAD.1996.568939},
doi = {10.1109/ICCAD.1996.568939},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LehtherS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/MaheshwariS96,
author = {Naresh Maheshwari and
Sachin S. Sapatnekar},
title = {A Practical Algorithm for Retiming Level-Clocked Circuits},
booktitle = {1996 International Conference on Computer Design {(ICCD} '96), {VLSI}
in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings},
pages = {440--445},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ICCD.1996.563591},
doi = {10.1109/ICCD.1996.563591},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/MaheshwariS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ShahS96,
author = {Jatan C. Shah and
Sachin S. Sapatnekar},
title = {Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs},
booktitle = {9th International Conference on {VLSI} Design {(VLSI} Design 1996),
3-6 January 1996, Bangalore, India},
pages = {346--351},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ICVD.1996.489633},
doi = {10.1109/ICVD.1996.489633},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ShahS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChuangSH95,
author = {Weitong Chuang and
Sachin S. Sapatnekar and
Ibrahim N. Hajj},
title = {Timing and area optimization for standard-cell {VLSI} circuit design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {14},
number = {3},
pages = {308--320},
year = {1995},
url = {https://doi.org/10.1109/43.365122},
doi = {10.1109/43.365122},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChuangSH95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DeokarS95,
author = {Rahul B. Deokar and
Sachin S. Sapatnekar},
editor = {Bryan Preas},
title = {A Fresh Look at Retiming Via Clock Skew Optimization},
booktitle = {Proceedings of the 32st Conference on Design Automation, San Francisco,
California, USA, Moscone Center, June 12-16, 1995},
pages = {310--315},
publisher = {{ACM} Press},
year = {1995},
url = {https://doi.org/10.1145/217474.217547},
doi = {10.1145/217474.217547},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DeokarS95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SapatnekarC95,
author = {Sachin S. Sapatnekar and
Weitong Chuang},
editor = {Richard L. Rudell},
title = {Power vs. delay in gate sizing: conflicting objectives?},
booktitle = {Proceedings of the 1995 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1995, San Jose, California, USA, November 5-9, 1995},
pages = {463--466},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1995},
url = {https://doi.org/10.1109/ICCAD.1995.480157},
doi = {10.1109/ICCAD.1995.480157},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SapatnekarC95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SathyamurthySF95,
author = {Harsha Sathyamurthy and
Sachin S. Sapatnekar and
John P. Fishburn},
editor = {Richard L. Rudell},
title = {Speeding up pipelined circuits through a combination of gate sizing
and clock skew optimization},
booktitle = {Proceedings of the 1995 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1995, San Jose, California, USA, November 5-9, 1995},
pages = {467--470},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1995},
url = {https://doi.org/10.1109/ICCAD.1995.480158},
doi = {10.1109/ICCAD.1995.480158},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SathyamurthySF95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SanchetiS95,
author = {Piyush K. Sancheti and
Sachin S. Sapatnekar},
title = {Layout Optimization Using Arbitrarily High Degree Posynomial Models},
booktitle = {1995 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
1995, Seattle, Washington, USA, April 30 - May 3, 1995},
pages = {53--56},
publisher = {{IEEE}},
year = {1995},
url = {https://doi.org/10.1109/ISCAS.1995.521449},
doi = {10.1109/ISCAS.1995.521449},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SanchetiS95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SapatnekarVK94,
author = {Sachin S. Sapatnekar and
Pravin M. Vaidya and
Sung{-}Mo Kang},
title = {Convexity-based algorithms for design centering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {13},
number = {12},
pages = {1536--1549},
year = {1994},
url = {https://doi.org/10.1109/43.331410},
doi = {10.1109/43.331410},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SapatnekarVK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Sapatnekar94,
author = {Sachin S. Sapatnekar},
editor = {Michael J. Lorenzetti},
title = {{RC} Interconnect Optimization Under the Elmore Delay Model},
booktitle = {Proceedings of the 31st Conference on Design Automation, San Diego,
California, USA, June 6-10, 1994},
pages = {387--391},
publisher = {{ACM} Press},
year = {1994},
url = {https://doi.org/10.1145/196244.196430},
doi = {10.1145/196244.196430},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/Sapatnekar94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/RamaswamySB94,
author = {Shankar Ramaswamy and
Sachin S. Sapatnekar and
Prithviraj Banerjee},
editor = {K. C. Tai},
title = {A Convex Programming Approach for Exploiting Data and Functional Parallelism
on Distributed Memory Multicomputers},
booktitle = {Proceedings of the 1994 International Conference on Parallel Processing,
North Carolina State University, NC, USA, August 15-19, 1994. Volume
{II:} Software},
pages = {116--125},
publisher = {{CRC} Press},
year = {1994},
url = {https://doi.org/10.1109/ICPP.1994.21},
doi = {10.1109/ICPP.1994.21},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/RamaswamySB94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KimKS94,
author = {Jaewon Kim and
Sung{-}Mo Kang and
Sachin S. Sapatnekar},
title = {High Performance {CMOS} Macromodule Layout Synthesis},
booktitle = {1994 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
1994, London, England, UK, May 30 - June 2, 1994},
pages = {179--182},
publisher = {{IEEE}},
year = {1994},
url = {https://doi.org/10.1109/ISCAS.1994.409219},
doi = {10.1109/ISCAS.1994.409219},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KimKS94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DeokarS94,
author = {Rahul B. Deokar and
Sachin S. Sapatnekar},
title = {A Graph-Theoretic Approach to Clock Skew Optimization},
booktitle = {1994 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
1994, London, England, UK, May 30 - June 2, 1994},
pages = {407--410},
publisher = {{IEEE}},
year = {1994},
url = {https://doi.org/10.1109/ISCAS.1994.408825},
doi = {10.1109/ISCAS.1994.408825},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DeokarS94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SapatnekarRVK93,
author = {Sachin S. Sapatnekar and
Vasant B. Rao and
Pravin M. Vaidya and
Sung{-}Mo Kang},
title = {An exact solution to the transistor sizing problem for {CMOS} circuits
using convex optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {12},
number = {11},
pages = {1621--1634},
year = {1993},
url = {https://doi.org/10.1109/43.248073},
doi = {10.1109/43.248073},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SapatnekarRVK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SapatnekarVK93,
author = {Sachin S. Sapatnekar and
Pravin M. Vaidya and
Steve M. Kang},
editor = {Michael R. Lightner and
Jochen A. G. Jess},
title = {Convexity-based algorithms for design centering},
booktitle = {Proceedings of the 1993 {IEEE/ACM} International Conference on Computer-Aided
Design, 1993, Santa Clara, California, USA, November 7-11, 1993},
pages = {206--209},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1993},
url = {https://doi.org/10.1109/ICCAD.1993.580057},
doi = {10.1109/ICCAD.1993.580057},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SapatnekarVK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChuangSH93,
author = {Weitong Chuang and
Sachin S. Sapatnekar and
Ibrahim N. Hajj},
editor = {Michael R. Lightner and
Jochen A. G. Jess},
title = {A unified algorithm for gate sizing and clock skew optimization to
minimize sequential circuit area},
booktitle = {Proceedings of the 1993 {IEEE/ACM} International Conference on Computer-Aided
Design, 1993, Santa Clara, California, USA, November 7-11, 1993},
pages = {220--223},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1993},
url = {https://doi.org/10.1109/ICCAD.1993.580060},
doi = {10.1109/ICCAD.1993.580060},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChuangSH93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SapatnekarVK93,
author = {Sachin S. Sapatnekar and
Pravin M. Vaidya and
Sung{-}Mo Kang},
title = {Feasible Region Approximation Using Convex Polytopes},
booktitle = {1993 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
1993, Chicago, Illinois, USA, May 3-6, 1993},
pages = {1786--1789},
publisher = {{IEEE}},
year = {1993},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SapatnekarVK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/us/Sapatnekar92,
author = {Sachin S. Sapatnekar},
title = {A Convex Programming Approach to Problems in {VLSI} Design},
school = {University of Illinois Urbana-Champaign, {USA}},
year = {1992},
url = {https://hdl.handle.net/2142/71984},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/us/Sapatnekar92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SapatnekarRV91,
author = {Sachin S. Sapatnekar and
Vasant B. Rao and
Pravin M. Vaidya},
title = {A Convex Optimization Approach to Transistor Sizing for {CMOS} Circuits},
booktitle = {1991 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of
Technical Papers},
pages = {482--485},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/ICCAD.1991.185310},
doi = {10.1109/ICCAD.1991.185310},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SapatnekarRV91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-25 05:57 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
