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ORCIDBibTeX records: Seng-Pan U
@article{DBLP:journals/tbcas/YinATSYYJWJU21,
author = {Yue Yin and
Syed Muhammad Abubakar and
Songyao Tan and
Jiahua Shi and
Peilin Yang and
Wendi Yang and
Hanjun Jiang and
Zhihua Wang and
Wen Jia and
Seng{-}Pan U},
title = {A 2.63 {\(\mu\)}W {ECG} Processor With Adaptive Arrhythmia Detection
and Data Compression for Implantable Cardiac Monitoring Device},
journal = {{IEEE} Trans. Biomed. Circuits Syst.},
volume = {15},
number = {4},
pages = {777--790},
year = {2021},
url = {https://doi.org/10.1109/TBCAS.2021.3100434},
doi = {10.1109/TBCAS.2021.3100434},
timestamp = {Tue, 05 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tbcas/YinATSYYJWJU21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AbubakarYTJWUJ21,
author = {Syed Muhammad Abubakar and
Yue Yin and
Songyao Tan and
Hanjun Jiang and
Zhihua Wang and
Seng{-}Pan U and
Wen Jia},
title = {A 2.52 {\(\mu\)}{\(\Alpha\)} Wearable Single Lead Ternary Neural Network
Based Cardiac Arrhythmia Detection Processor},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401054},
doi = {10.1109/ISCAS51556.2021.9401054},
timestamp = {Fri, 30 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AbubakarYTJWUJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DalyLYBMMMWU21,
author = {Denis Daly and
Zeynep Lulec and
Rabia Tugce Yazicigil and
Alison J. Burdett and
Rituparna Mandal and
Matheus Moreira and
Dante G. Muratore and
Aisha Walcott{-}Bryant and
Ben Seng{-}Pan U},
title = {{SE5:} Making a Career Choice},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {546--547},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365952},
doi = {10.1109/ISSCC42613.2021.9365952},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/DalyLYBMMMWU21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/YinATJWUJ20,
author = {Yue Yin and
Syed Muhammad Abubakar and
Songyao Tan and
Hanjun Jiang and
Zhihua Wang and
Seng{-}Pan U and
Wen Jia},
title = {A 17.7-pJ/Cycle {ECG} Processor for Arrhythmia Detection with High
Immunity to Power Line Interference and Baseline Drift},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2020, Virtual
Event, Japan, November 9-11, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/A-SSCC48613.2020.9336104},
doi = {10.1109/A-SSCC48613.2020.9336104},
timestamp = {Fri, 30 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/YinATJWUJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WangSUMM19,
author = {Biao Wang and
Sai{-}Weng Sin and
Seng{-}Pan U and
Franco Maloberti and
Rui Paulo Martins},
title = {A 550- {\textdollar}{\textbackslash}mu{\textdollar} {W} 20-kHz {BW}
100.8-dB {SNDR} Linear- Exponential Multi-Bit Incremental {\textdollar}{\textbackslash}Sigma{\textbackslash}Delta{\textdollar}
{ADC} With 256 Clock Cycles in 65-nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {4},
pages = {1161--1172},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2888872},
doi = {10.1109/JSSC.2018.2888872},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/WangSUMM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/Xing0CMUM19,
author = {Dezhi Xing and
Yan Zhu and
Chi{-}Hang Chan and
Franco Maloberti and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Design of a High-Speed Time-Interleaved Sub-Ranging {SAR} {ADC} With
Optimal Code Transfer Technique},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {66-I},
number = {2},
pages = {489--501},
year = {2019},
url = {https://doi.org/10.1109/TCSI.2018.2866958},
doi = {10.1109/TCSI.2018.2866958},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/Xing0CMUM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuCSUM19,
author = {Jianwei Liu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Accuracy-Enhanced Variance-Based Time-Skew Calibration Using {SAR}
as Window Detector},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {481--485},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2874772},
doi = {10.1109/TVLSI.2018.2874772},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuCSUM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/WangSUMM19,
author = {Biao Wang and
Sai{-}Weng Sin and
Seng{-}Pan U and
Franco Maloberti and
Rui Paulo Martins},
title = {A 1.2V 86dB {SNDR} 500kHz {BW} Linear-Exponential Multi-Bit Incremental
{ADC} Using Positive Feedback in 65nm {CMOS}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2019, Macau,
SAR, China, November 4-6, 2019},
pages = {117--120},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/A-SSCC47793.2019.9056948},
doi = {10.1109/A-SSCC47793.2019.9056948},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/WangSUMM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/LiangSUMMJ19,
author = {Junhao Liang and
Sai{-}Weng Sin and
Seng{-}Pan U and
Franco Maloberti and
Rui Paulo Martins and
Hanjun Jiang},
title = {A High {DR} High-Input-Impedance Programmable-Gain {ECG} Acquisition
Interface with Non-inverting Continuous Time Sigma-Delta Modulator},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2019, Macau,
SAR, China, November 4-6, 2019},
pages = {309--312},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/A-SSCC47793.2019.9056891},
doi = {10.1109/A-SSCC47793.2019.9056891},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/LiangSUMMJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HuangLUM18,
author = {Mo Huang and
Yan Lu and
Seng{-}Pan U and
Rui Paulo Martins},
title = {An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {1},
pages = {20--34},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2017.2751512},
doi = {10.1109/JSSC.2017.2751512},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HuangLUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChanZZUM18,
author = {Chi{-}Hang Chan and
Yan Zhu and
Wai{-}Hong Zhang and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle {SAR} {ADC} With
Background Offset Calibration},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {3},
pages = {850--860},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2017.2785349},
doi = {10.1109/JSSC.2017.2785349},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChanZZUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/QinSUM18,
author = {Wei Wei Qin and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Quick and cost-efficient {A/D} converter static characterization using
low-precision testing signal},
journal = {Microelectron. J.},
volume = {74},
pages = {86--93},
year = {2018},
url = {https://doi.org/10.1016/j.mejo.2018.02.001},
doi = {10.1016/J.MEJO.2018.02.001},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/QinSUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/YangZCUM18,
author = {Xiaofeng Yang and
Yan Zhu and
Chi{-}Hang Chan and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Analysis of Common-Mode Interference and Jitter of Clock Receiver
Circuits With Improved Topology},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {65-I},
number = {6},
pages = {1819--1829},
year = {2018},
url = {https://doi.org/10.1109/TCSI.2017.2766527},
doi = {10.1109/TCSI.2017.2766527},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/YangZCUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongCZGUM18,
author = {Yan Song and
Chi{-}Hang Chan and
Yan Zhu and
Li Geng and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Passive Noise Shaping in {SAR} {ADC} With Improved Efficiency},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {416--420},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2764742},
doi = {10.1109/TVLSI.2017.2764742},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SongCZGUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QiuTZSZU18,
author = {Lei Qiu and
Kai Tang and
Yuanjin Zheng and
Liter Siek and
Yan Zhu and
Seng{-}Pan U},
title = {A 16-mW 1-GS/s With 49.6-dB {SNDR} {TI-SAR} {ADC} for Software-Defined
Radio in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {3},
pages = {572--583},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2771811},
doi = {10.1109/TVLSI.2017.2771811},
timestamp = {Tue, 11 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/QiuTZSZU18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZCUM18,
author = {Guan{-}Cheng Wang and
Yan Zhu and
Chi{-}Hang Chan and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Gain Error Calibrations for Two-Step ADCs: Optimizations Either in
Accuracy or Chip Area},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2279--2289},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2865595},
doi = {10.1109/TVLSI.2018.2865595},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZCUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Jiang0LKMUM18,
author = {Junmin Jiang and
Yan Lu and
Xun Liu and
Wing{-}Hung Ki and
Philip K. T. Mok and
Seng{-}Pan U and
Rui Paulo Martins},
editor = {Youngsoo Shin},
title = {A dual-output {SC} converter with dynamic power allocation for multicore
application processors},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {285--286},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297322},
doi = {10.1109/ASPDAC.2018.8297322},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/Jiang0LKMUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/Jiang0CMUM18,
author = {Wenning Jiang and
Yan Zhu and
Chi{-}Hang Chan and
Boris Murmann and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 7b 2 GS/s Time-Interleaved {SAR} {ADC} with Time Skew Calibration
Based on Current Integrating Sampler},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
Taiwan, November 5-7, 2018},
pages = {235--238},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASSCC.2018.8579344},
doi = {10.1109/ASSCC.2018.8579344},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/Jiang0CMUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MaoLLZUM18,
author = {Fangyu Mao and
Yan Lu and
Jie Lin and
Chenchang Zhan and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current
Regulation for IoT},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8351692},
doi = {10.1109/ISCAS.2018.8351692},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MaoLLZUM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/Mao0UM18,
author = {Fangyu Mao and
Yan Lu and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A reconfigurable cross-connected wireless-power transceiver for bidirectional
device-to-device charging with 78.1{\%} total efficiency},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {140--142},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310223},
doi = {10.1109/ISSCC.2018.8310223},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/Mao0UM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/Mao0UM18,
author = {Fangyu Mao and
Yan Lu and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation
for wireless power transfer systems},
booktitle = {2018 International Symposium on {VLSI} Design, Automation and Test
(VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-DAT.2018.8373261},
doi = {10.1109/VLSI-DAT.2018.8373261},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/Mao0UM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WangSUMM18,
author = {Biao Wang and
Sai{-}Weng Sin and
Seng{-}Pan U and
Franco Maloberti and
Rui Paulo Martins},
title = {A 550{\(\mathrm{\mu}\)}W 20kHz {BW} 100.8DB {SNDR} Linear-Exponential
Multi-Bit Incremental Converter with 256-cycles in 65NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {207--208},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502384},
doi = {10.1109/VLSIC.2018.8502384},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/WangSUMM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChanZLZHWUM17,
author = {Chi{-}Hang Chan and
Yan Zhu and
Cheng Li and
Wai{-}Hong Zhang and
Iok{-}Meng Ho and
Lai Wei and
Seng{-}Pan U and
Rui Paulo Martins},
title = {60-dB {SNDR} 100-MS/s {SAR} ADCs With Threshold Reconfigurable Reference
Error Calibration},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {10},
pages = {2576--2588},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2017.2728784},
doi = {10.1109/JSSC.2017.2728784},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChanZLZHWUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/LuoLHJSUM17,
author = {Ziyang Luo and
Yan Lu and
Mo Huang and
Junmin Jiang and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A sub-1V 78-nA bandgap reference with curvature compensation},
journal = {Microelectron. J.},
volume = {63},
pages = {35--40},
year = {2017},
url = {https://doi.org/10.1016/j.mejo.2017.02.016},
doi = {10.1016/J.MEJO.2017.02.016},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/LuoLHJSUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChanZSMUM17,
author = {Chi{-}Hang Chan and
Yan Zhu and
Sai{-}Weng Sin and
Boris Murmann and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Metastablility in {SAR} ADCs},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {64-II},
number = {2},
pages = {111--115},
year = {2017},
url = {https://doi.org/10.1109/TCSII.2016.2554798},
doi = {10.1109/TCSII.2016.2554798},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/ChanZSMUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LuDHLSUM17,
author = {Yan Lu and
Haojuan Dai and
Mo Huang and
Man{-}Kay Law and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A Wide Input Range Dual-Path {CMOS} Rectifier for {RF} Energy Harvesting},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {64-II},
number = {2},
pages = {166--170},
year = {2017},
url = {https://doi.org/10.1109/TCSII.2016.2554778},
doi = {10.1109/TCSII.2016.2554778},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/LuDHLSUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ZhongZCSUM17,
author = {Jianyu Zhong and
Yan Zhu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 12b 180MS/s 0.068mm\({}^{\mbox{2}}\) With Full-Calibration-Integrated
Pipelined-SAR {ADC}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {64-I},
number = {7},
pages = {1684--1695},
year = {2017},
url = {https://doi.org/10.1109/TCSI.2017.2679748},
doi = {10.1109/TCSI.2017.2679748},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/ZhongZCSUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChanZSUMM17,
author = {Chi{-}Hang Chan and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins and
Franco Maloberti},
title = {A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash {ADC}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {64-I},
number = {8},
pages = {1966--1976},
year = {2017},
url = {https://doi.org/10.1109/TCSI.2017.2682268},
doi = {10.1109/TCSI.2017.2682268},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/ChanZSUMM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/QiSUMM17,
author = {Liang Qi and
Sai{-}Weng Sin and
Seng{-}Pan U and
Franco Maloberti and
Rui Paulo Martins},
title = {A 4.2-mW 77.1-dB {SNDR} 5-MHz {BW} {DT} 2-1 {MASH} {\(\Delta\)} {\(\Sigma\)}
Modulator With Multirate Opamp Sharing},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {64-I},
number = {10},
pages = {2641--2654},
year = {2017},
url = {https://doi.org/10.1109/TCSI.2017.2693921},
doi = {10.1109/TCSI.2017.2693921},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/QiSUMM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/0001CUM17,
author = {Yan Zhu and
Chi{-}Hang Chan and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 10-bit 500-MS/s Partial-Interleaving Pipelined {SAR} {ADC} With
Offset and Reference Mismatch Calibrations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {354--363},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2576468},
doi = {10.1109/TVLSI.2016.2576468},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/0001CUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HussainSCUMM17,
author = {Arshad Hussain and
Sai{-}Weng Sin and
Chi{-}Hang Chan and
Ben Seng{-}Pan U and
Franco Maloberti and
Rui Paulo Martins},
title = {Active-Passive {\(\Delta\)}{\(\Sigma\)} Modulator for High-Resolution
and Low-Power Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {364--374},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2580712},
doi = {10.1109/TVLSI.2016.2580712},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HussainSCUMM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XingZCSYRUM17,
author = {Dezhi Xing and
Yan Zhu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Fan Ye and
Junyan Ren and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Seven-bit 700-MS/s Four-Way Time-Interleaved {SAR} {ADC} With Partial
{\textdollar}V{\_}\{{\textbackslash}mathrm \{cm\}\}{\textdollar} -Based
Switching},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1168--1172},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2610864},
doi = {10.1109/TVLSI.2016.2610864},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XingZCSYRUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/ChioSUMM17,
author = {U. Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U and
Franco Maloberti and
Rui Paulo Martins},
title = {A 5-bit 2 GS/s binary-search {ADC} with charge-steering comparators},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
Korea (South), November 6-8, 2017},
pages = {221--224},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASSCC.2017.8240256},
doi = {10.1109/ASSCC.2017.8240256},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/ChioSUMM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/WangZCUM17,
author = {Wei Wang and
Yan Zhu and
Chi{-}Hang Chan and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 5.35 mW 10 MHz bandwidth {CT} third-order {\(\Delta\)}{\(\Sigma\)}
modulator with single Opamp achieving 79.6/84.5 dB {SNDR/DR} in 65
nm {CMOS}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
Korea (South), November 6-8, 2017},
pages = {285--288},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASSCC.2017.8240272},
doi = {10.1109/ASSCC.2017.8240272},
timestamp = {Fri, 16 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/WangZCUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/Wang0CUM17,
author = {Guan{-}Cheng Wang and
Yan Zhu and
Chi{-}Hang Chan and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A missing-code-detection gain error calibration achieving 63dB {SNR}
for an 11-bit {ADC}},
booktitle = {43rd {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2017,
Leuven, Belgium, September 11-14, 2017},
pages = {239--242},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ESSCIRC.2017.8094570},
doi = {10.1109/ESSCIRC.2017.8094570},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/Wang0CUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/ULLSWUM17,
author = {Chi{-}Wa U and
Chi{-}Seng Lam and
Man{-}Kay Law and
Sai{-}Weng Sin and
Man{-}Chung Wong and
Seng{-}Pan U and
Rui Paulo Martins},
title = {{CCM} operation analysis and parameters design of Negative Output
Elementary Luo Converter for ripple suppression},
booktitle = {{IECON} 2017 - 43rd Annual Conference of the {IEEE} Industrial Electronics
Society, Beijing, China, October 29 - November 1, 2017},
pages = {4867--4871},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/IECON.2017.8216840},
doi = {10.1109/IECON.2017.8216840},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iecon/ULLSWUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isie/DuLSLMWUM17,
author = {Xia Du and
Chi{-}Seng Lam and
Sai{-}Weng Sin and
Man{-}Kay Law and
Franco Maloberti and
Man{-}Chung Wong and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A digital {PWM} controlled {KY} step-up converter based on frequency
domain {\(\Sigma\)}{\(\Delta\)} {ADC}},
booktitle = {26th {IEEE} International Symposium on Industrial Electronics, {ISIE}
2017, Edinburgh, United Kingdom, June 19-21, 2017},
pages = {561--564},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISIE.2017.8001307},
doi = {10.1109/ISIE.2017.8001307},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isie/DuLSLMWUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/Chan0HZUM17,
author = {Chi{-}Hang Chan and
Yan Zhu and
Iok{-}Meng Ho and
Wai{-}Hong Zhang and
Seng{-}Pan U and
Rui Paulo Martins},
title = {16.4 {A} 5mW 7b 2.4GS/s 1-then-2b/cycle {SAR} {ADC} with background
offset calibration},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {282--283},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870371},
doi = {10.1109/ISSCC.2017.7870371},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/Chan0HZUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HuangLUM17,
author = {Mo Huang and
Yan Lu and
Seng{-}Pan U and
Rui Paulo Martins},
title = {20.4 An output-capacitor-free analog-assisted digital low-dropout
regulator with tri-loop control},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {342--343},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870401},
doi = {10.1109/ISSCC.2017.7870401},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/HuangLUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/JiangLKUM17,
author = {Junmin Jiang and
Yan Lu and
Wing{-}Hung Ki and
Seng{-}Pan U and
Rui Paulo Martins},
title = {20.5 {A} dual-symmetrical-output switched-capacitor converter with
dynamic power cells and minimized cross regulation for application
processors in 28nm {CMOS}},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {344--345},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870402},
doi = {10.1109/ISSCC.2017.7870402},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/JiangLKUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HuangLUM17a,
author = {Mo Huang and
Yan Lu and
Seng{-}Pan U and
Rui Paulo Martins},
title = {22.4 {A} reconfigurable bidirectional wireless power transceiver with
maximum-current charging mode and 58.6{\%} battery-to-battery efficiency},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {376--377},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870418},
doi = {10.1109/ISSCC.2017.7870418},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/HuangLUM17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DorisRRS17,
author = {Kostas Doris and
David Robertson and
Seung{-}Tak Ryu and
Seng{-}Pan U},
title = {{F6:} Pushing the performance limit in data converters organizers:
Venkatesh Srinivasan, Texas Instruments, Dallas, {TX}},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {515--517},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870484},
doi = {10.1109/ISSCC.2017.7870484},
timestamp = {Thu, 12 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/DorisRRS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/Chan0SUM16,
author = {Chi{-}Hang Chan and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 6 b 5 GS/s 4 Interleaved 3 b/Cycle {SAR} {ADC}},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {2},
pages = {365--377},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2015.2493167},
doi = {10.1109/JSSC.2015.2493167},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/Chan0SUM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ZhuCUM16,
author = {Yan Zhu and
Chi{-}Hang Chan and
Seng{-}Pan U and
Rui Paulo Martins},
title = {An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR
{ADC} in 65 nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {5},
pages = {1223--1234},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2016.2522762},
doi = {10.1109/JSSC.2016.2522762},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ZhuCUM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/HuangLSUM16,
author = {Mo Huang and
Yan Lu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A Fully Integrated Digital {LDO} With Coarse-Fine-Tuning and Burst-Mode
Operation},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {63-II},
number = {7},
pages = {683--687},
year = {2016},
url = {https://doi.org/10.1109/TCSII.2016.2530094},
doi = {10.1109/TCSII.2016.2530094},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/HuangLSUM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/HuangLSUMK16,
author = {Mo Huang and
Yan Lu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins and
Wing{-}Hung Ki},
title = {Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {63-II},
number = {9},
pages = {903--907},
year = {2016},
url = {https://doi.org/10.1109/TCSII.2016.2534778},
doi = {10.1109/TCSII.2016.2534778},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/HuangLSUMK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/0001CWUM16,
author = {Yan Zhu and
Chi{-}Hang Chan and
Si{-}Seng Wong and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit
120 MS/s {SAR} {ADC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {3},
pages = {1203--1207},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2442258},
doi = {10.1109/TVLSI.2015.2442258},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/0001CWUM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Liu0CSUM16,
author = {Jianwei Liu and
Yan Zhu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo da Silva Martins},
title = {Uniform Quantization Theory-Based Linearity Calibration for Split
Capacitive {DAC} in an {SAR} {ADC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {7},
pages = {2603--2607},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2509164},
doi = {10.1109/TVLSI.2015.2509164},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Liu0CSUM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/HuangLUM16,
author = {Mo Huang and
Yan Lu and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A digital {LDO} with transient enhancement and limit cycle oscillation
reduction},
booktitle = {2016 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2016, Jeju, South Korea, October 25-28, 2016},
pages = {25--28},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/APCCAS.2016.7803886},
doi = {10.1109/APCCAS.2016.7803886},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/HuangLUM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/RenSLWUM16,
author = {Yuan Ren and
Sai{-}Weng Sin and
Chi{-}Seng Lam and
Man{-}Chung Wong and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A high {DR} multi-channel stage-shared hybrid front-end for integrated
power electronics controller},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
Japan, November 7-9, 2016},
pages = {57--60},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASSCC.2016.7844134},
doi = {10.1109/ASSCC.2016.7844134},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/RenSLWUM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/QiuTZSZU16,
author = {Lei Qiu and
Kai Tang and
Yan Zhu and
Liter Siek and
Yuanjin Zheng and
Seng{-}Pan U},
title = {A 10-bit 1GS/s 4-way {TI} {SAR} {ADC} with tap-interpolated {FIR}
filter based time skew calibration},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
Japan, November 7-9, 2016},
pages = {77--80},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASSCC.2016.7844139},
doi = {10.1109/ASSCC.2016.7844139},
timestamp = {Tue, 11 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/QiuTZSZU16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/Chan0HZLUM16,
author = {Chi{-}Hang Chan and
Yan Zhu and
Iok{-}Meng Ho and
Wai{-}Hong Zhang and
Chon{-}Lam Lio and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 0.011mm\({}^{\mbox{2}}\) 60dB {SNDR} 100MS/s reference error calibrated
{SAR} {ADC} with 3pF decoupling capacitance for reference voltages},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
Japan, November 7-9, 2016},
pages = {145--148},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASSCC.2016.7844156},
doi = {10.1109/ASSCC.2016.7844156},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/Chan0HZLUM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/Zhong0CSUM16,
author = {Jianyu Zhong and
Yan Zhu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 12b 180MS/s 0.068mm\({}^{\mbox{2}}\) pipelined-SAR {ADC} with merged-residue
{DAC} for noise reduction},
booktitle = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State
Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
pages = {169--172},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ESSCIRC.2016.7598269},
doi = {10.1109/ESSCIRC.2016.7598269},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/Zhong0CSUM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isicir/LiSUM16,
author = {Wei Li and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation
applications},
booktitle = {International Symposium on Integrated Circuits, {ISIC} 2016, Singapore,
December 12-14, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISICIR.2016.7829723},
doi = {10.1109/ISICIR.2016.7829723},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isicir/LiSUM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/Zhong0SUM15,
author = {Jianyu Zhong and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Thermal and Reference Noise Analysis of Time-Interleaving {SAR} and
Partial-Interleaving Pipelined-SAR ADCs},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {62-I},
number = {9},
pages = {2196--2206},
year = {2015},
url = {https://doi.org/10.1109/TCSI.2015.2452331},
doi = {10.1109/TCSI.2015.2452331},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/Zhong0SUM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/LiuCSUM15,
author = {Jianwei Liu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 89fJ-FOM 6-bit 3.4GS/s flash {ADC} with 4x time-domain interpolation},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2015, Xia'men,
China, November 9-11, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASSCC.2015.7387463},
doi = {10.1109/ASSCC.2015.7387463},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/LiuCSUM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/Chan0SUM15,
author = {Chi{-}Hang Chan and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {26.5 {A} 5.5mW 6b 5GS/S 4{\texttimes}-lnterleaved 3b/cycle {SAR} {ADC}
in 65nm {CMOS}},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7063128},
doi = {10.1109/ISSCC.2015.7063128},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/Chan0SUM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LuJKYSUM15,
author = {Yan Lu and
Junmin Jiang and
Wing{-}Hung Ki and
C. Patrick Yue and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {20.4 {A} 123-phase {DC-DC} converter-ring with fast-DVS for microprocessors},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7063077},
doi = {10.1109/ISSCC.2015.7063077},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/LuJKYSUM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuCCSUMM14,
author = {Yan Zhu and
Chi{-}Hang Chan and
U. Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins and
Franco Maloberti},
title = {Split-SAR ADCs: Improved Linearity With Power and Speed Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {2},
pages = {372--383},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2242501},
doi = {10.1109/TVLSI.2013.2242501},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuCCSUMM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/0001CUM14,
author = {Yan Zhu and
Chi{-}Hang Chan and
Seng{-}Pan U and
Rui Paulo Martins},
title = {An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR {ADC}},
booktitle = {{ESSCIRC} 2014 - 40th European Solid State Circuits Conference, Venice
Lido, Italy, September 22-26, 2014},
pages = {211--214},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ESSCIRC.2014.6942059},
doi = {10.1109/ESSCIRC.2014.6942059},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/0001CUM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/FengMSUM14,
author = {Da Feng and
Franco Maloberti and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Jitter-resistant Capacitor Based Sine-Shaped {DAC} for Continuous-Time
Sigma-Delta modulators},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {1348--1351},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865393},
doi = {10.1109/ISCAS.2014.6865393},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/FengMSUM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WongCZSUM13,
author = {Si{-}Seng Wong and
U{-}Fat Chio and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved
{SAR} {ADC}},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {8},
pages = {1783--1794},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2013.2258832},
doi = {10.1109/JSSC.2013.2258832},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/WongCZSUM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChanZSUMM13,
author = {Chi{-}Hang Chan and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins and
Franco Maloberti},
title = {A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash {ADC} in 65-nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {9},
pages = {2154--2169},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2013.2264617},
doi = {10.1109/JSSC.2013.2264617},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChanZSUMM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DuHJSUM13,
author = {Yun Du and
Tao He and
Yang Jiang and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A continuous-time VCO-assisted VCO-based {\(\Sigma\)}{\(\Delta\)}
modulator with 76.6dB {SNDR} and 10MHz {BW}},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {373--376},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6571858},
doi = {10.1109/ISCAS.2013.6571858},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/DuHJSUM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WuZDCCSUM13,
author = {Wen{-}Lan Wu and
Yan Zhu and
Li Ding and
Chi{-}Hang Chan and
U. Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A 0.6V 8b 100MS/s {SAR} {ADC} with minimized {DAC} capacitance and
switching energy in 65nm {CMOS}},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {2239--2242},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6572322},
doi = {10.1109/ISCAS.2013.6572322},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/WuZDCCSUM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/DingSUM13,
author = {Li Ding and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A background gain- calibration technique for low voltage pipelined
ADCs based on nonlinear interpolation},
booktitle = {{IEEE} 56th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2013, Columbus, OH, USA, August 4-7, 2013},
pages = {665--668},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/MWSCAS.2013.6674736},
doi = {10.1109/MWSCAS.2013.6674736},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/DingSUM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ZhuCSUMM12,
author = {Yan Zhu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins and
Franco Maloberti},
title = {A 50-fJ 10-b 160-MS/s Pipelined-SAR {ADC} Decoupled Flip-Around {MDAC}
and Self-Embedded Offset Cancellation},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {11},
pages = {2614--2626},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2211695},
doi = {10.1109/JSSC.2012.2211695},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ZhuCSUMM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WeiCCSUMM12,
author = {He Gong Wei and
Chi{-}Hang Chan and
U. Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins and
Franco Maloberti},
title = {An 8-b 400-MS/s 2-b-Per-Cycle {SAR} {ADC} With Resistive {DAC}},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {11},
pages = {2763--2772},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2214181},
doi = {10.1109/JSSC.2012.2214181},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/WeiCCSUMM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/DuHJSUM12,
author = {Yun Du and
Tao He and
Yang Jiang and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A robust {NTF} zero optimization technique for both low and high OSRs
sigma-delta modulators},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2012,
Kaohsiung, Taiwan, December 2-5, 2012},
pages = {29--32},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/APCCAS.2012.6418963},
doi = {10.1109/APCCAS.2012.6418963},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/DuHJSUM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/HeDJSUM12,
author = {Tao He and
Yun Du and
Yang Jiang and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A {DT} 0-2 {MASH} {\(\Sigma\)}{\(\Delta\)} modulator with VCO-based
quantizer for enhanced linearity},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2012,
Kaohsiung, Taiwan, December 2-5, 2012},
pages = {33--36},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/APCCAS.2012.6418964},
doi = {10.1109/APCCAS.2012.6418964},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/HeDJSUM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/WuSUM12,
author = {Wen{-}Lan Wu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 10-bit {SAR} {ADC} with two redundant decisions and splitted-MSB-cap
{DAC} array},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2012,
Kaohsiung, Taiwan, December 2-5, 2012},
pages = {268--271},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/APCCAS.2012.6419023},
doi = {10.1109/APCCAS.2012.6419023},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/WuSUM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/WongCZSUM12,
author = {Si{-}Seng Wong and
U{-}Fat Chio and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved
{SAR} {ADC}},
booktitle = {Proceedings of the {IEEE} 2012 Custom Integrated Circuits Conference,
{CICC} 2012, San Jose, CA, USA, September 9-12, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/CICC.2012.6330695},
doi = {10.1109/CICC.2012.6330695},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/WongCZSUM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/WangCSUWM12,
author = {Rui Wang and
U{-}Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Zhihua Wang and
Rui Paulo Martins},
title = {A 12-bit 110MS/s 4-stage single-opamp pipelined {SAR} {ADC} with ratio-based
{GEC} technique},
booktitle = {Proceedings of the 38th European Solid-State Circuit conference, {ESSCIRC}
2012, Bordeaux, France, September 17-21, 2012},
pages = {265--268},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ESSCIRC.2012.6341336},
doi = {10.1109/ESSCIRC.2012.6341336},
timestamp = {Fri, 30 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/WangCSUWM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/YinWCSUWM12,
author = {Guohe Yin and
He Gong Wei and
U{-}Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Zhihua Wang and
Rui Paulo Martins},
title = {A 0.024 mm\({}^{\mbox{2}}\) 4.9 fJ 10-bit 2 MS/s {SAR} {ADC} in 65
nm {CMOS}},
booktitle = {Proceedings of the 38th European Solid-State Circuit conference, {ESSCIRC}
2012, Bordeaux, France, September 17-21, 2012},
pages = {377--380},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ESSCIRC.2012.6341364},
doi = {10.1109/ESSCIRC.2012.6341364},
timestamp = {Fri, 30 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/YinWCSUWM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HeJDSUM12,
author = {Tao He and
Yang Jiang and
Yun Du and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A 10MHz {BW} 78dB {DR} {CT} {\(\Sigma\)}{\(\Delta\)} modulator with
novel switched high linearity VCO-based quantizer},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {65--68},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6272116},
doi = {10.1109/ISCAS.2012.6272116},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/HeJDSUM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/Cai0SUM12,
author = {Chen{-}Yan Cai and
Yang Jiang and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {An {ELD} tracking compensation technique for active-RC {CT} {\(\Sigma\)}{\(\Delta\)}
modulators},
booktitle = {55th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2012, Boise, ID, USA, August 5-8, 2012},
pages = {1096--1099},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/MWSCAS.2012.6292215},
doi = {10.1109/MWSCAS.2012.6292215},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/Cai0SUM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Chan0SUM12,
author = {Chi{-}Hang Chan and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 3.8mW 8b 1GS/s 2b/cycle interleaving {SAR} {ADC} with compact {DAC}
structure},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {86--87},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243802},
doi = {10.1109/VLSIC.2012.6243802},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Chan0SUM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/0001CSUM12,
author = {Yan Zhu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 34fJ 10b 500 MS/s partial-interleaving pipelined {SAR} {ADC}},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {90--91},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243804},
doi = {10.1109/VLSIC.2012.6243804},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/0001CSUM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/0001CSUMM11,
author = {Yan Zhu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins and
Franco Maloberti},
title = {A 35 fJ 10b 160 MS/s pipelined-SAR {ADC} with decoupled flip-around
{MDAC} and self-embedded offset cancellation},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
South Korea, November 14-16, 2011},
pages = {61--64},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASSCC.2011.6123604},
doi = {10.1109/ASSCC.2011.6123604},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/0001CSUMM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/WongCCCSUM11,
author = {Si{-}Seng Wong and
U. Fat Chio and
Chi{-}Hang Chan and
Hou{-}Lon Choi and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 4.8-bit {ENOB} 5-bit 500MS/s binary-search {ADC} with minimized
number of comparators},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
South Korea, November 14-16, 2011},
pages = {73--76},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASSCC.2011.6123607},
doi = {10.1109/ASSCC.2011.6123607},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/WongCCCSUM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/Chan0CSUM11,
author = {Chi{-}Hang Chan and
Yan Zhu and
U. Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A reconfigurable low-noise dynamic comparator with offset calibration
in 90nm {CMOS}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
South Korea, November 14-16, 2011},
pages = {233--236},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASSCC.2011.6123645},
doi = {10.1109/ASSCC.2011.6123645},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/Chan0CSUM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/ChioCCSUM11,
author = {U. Fat Chio and
Chi{-}Hang Chan and
Hou{-}Lon Choi and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A 7-bit 300-MS/s subranging {ADC} with embedded threshold {\&}
gain-loss calibration},
booktitle = {Proceedings of the 37th European Solid-State Circuits Conference,
{ESSCIRC} 2011, Helsinki, Finland, Sept. 12-16, 2011},
pages = {363--366},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ESSCIRC.2011.6044982},
doi = {10.1109/ESSCIRC.2011.6044982},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/ChioCCSUM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/HussainSUM11,
author = {Arshad Hussain and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Hybrid loopfilter sigma-delta modulator with {NTF} zero compensation},
booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
November 17-18, 2011},
pages = {76--79},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISOCC.2011.6138650},
doi = {10.1109/ISOCC.2011.6138650},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/HussainSUM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WeiCCSSMM11,
author = {He Gong Wei and
Chi{-}Hang Chan and
U{-}Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins and
Franco Maloberti},
title = {A 0.024mm\({}^{\mbox{2}}\) 8b 400MS/s {SAR} {ADC} with 2b/cycle and
resistive {DAC} in 65nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {188--190},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746276},
doi = {10.1109/ISSCC.2011.5746276},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/WeiCCSSMM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/SinUM10,
author = {Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital
converter in 0.18 {\(\mu\)}m {CMOS} with minimised supply headroom},
journal = {{IET} Circuits Devices Syst.},
volume = {4},
number = {1},
pages = {1--13},
year = {2010},
url = {https://doi.org/10.1049/iet-cds.2008.0229},
doi = {10.1049/IET-CDS.2008.0229},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cds/SinUM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ZhuCCSUMM10,
author = {Yan Zhu and
Chi{-}Hang Chan and
U. Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins and
Franco Maloberti},
title = {A 10-bit 100-MS/s Reference-Free {SAR} {ADC} in 90 nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {45},
number = {6},
pages = {1111--1121},
year = {2010},
url = {https://doi.org/10.1109/JSSC.2010.2048498},
doi = {10.1109/JSSC.2010.2048498},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ZhuCCSUMM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/WeiCZSUM10,
author = {He Gong Wei and
U{-}Fat Chio and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm {CMOS}},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {57-II},
number = {1},
pages = {16--20},
year = {2010},
url = {https://doi.org/10.1109/TCSII.2009.2037260},
doi = {10.1109/TCSII.2009.2037260},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/WeiCZSUM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChioWZSUMM10,
author = {U{-}Fat Chio and
He Gong Wei and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins and
Franco Maloberti},
title = {Design and Experimental Verification of a Power Effective Flash-SAR
Subranging {ADC}},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {57-II},
number = {8},
pages = {607--611},
year = {2010},
url = {https://doi.org/10.1109/TCSII.2010.2050937},
doi = {10.1109/TCSII.2010.2050937},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/ChioWZSUMM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ZhuCWSUM10,
author = {Yan Zhu and
U. Fat Chio and
He Gong Wei and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {Linearity Analysis on a Series-Split Capacitor Array for High-Speed
{SAR} ADCs},
journal = {{VLSI} Design},
volume = {2010},
pages = {706548:1--706548:8},
year = {2010},
url = {https://doi.org/10.1155/2010/706548},
doi = {10.1155/2010/706548},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/ZhuCWSUM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/DingSUM10,
author = {Li Ding and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {An efficient {DAC} and interstage gain error calibration technique
for multi-bit pipelined ADCs},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
Kuala Lumpur, Malaysia, December 6-9, 2010},
pages = {208--211},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/APCCAS.2010.5774899},
doi = {10.1109/APCCAS.2010.5774899},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/DingSUM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/JiangWCSUM10,
author = {Yang Jiang and
Kim{-}Fai Wong and
Chen{-}Yan Cai and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A reduced jitter-sensitivity clock generation technique for continuous-time
{\(\Sigma\)}{\(\Delta\)} modulators},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
Kuala Lumpur, Malaysia, December 6-9, 2010},
pages = {1011--1014},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/APCCAS.2010.5774943},
doi = {10.1109/APCCAS.2010.5774943},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/JiangWCSUM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/SinDZWCCUMM10,
author = {Sai{-}Weng Sin and
Li Ding and
Yan Zhu and
He Gong Wei and
Chi{-}Hang Chan and
U. Fat Chio and
Seng{-}Pan U and
Rui Paulo Martins and
Franco Maloberti},
title = {An 11b 60MS/s 2.1mW two-step time-interleaved {SAR-ADC} with reused
S{\&}H},
booktitle = {36th European Solid-State Circuits Conference, {ESSCIRC} 2010, Sevilla,
Spain, September 13-17, 2010},
pages = {218--221},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ESSCIRC.2010.5619890},
doi = {10.1109/ESSCIRC.2010.5619890},
timestamp = {Mon, 09 Aug 2021 14:54:02 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/SinDZWCCUMM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/JiangWCSUM10,
author = {Yang Jiang and
Kim{-}Fai Wong and
Chen{-}Yan Cai and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity
in Continuous-Time sigma-delta modulators},
booktitle = {17th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2010, Athens, Greece, 12-15 December, 2010},
pages = {547--550},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICECS.2010.5724570},
doi = {10.1109/ICECS.2010.5724570},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/JiangWCSUM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/YinCWSUMW10,
author = {Guohe Yin and
U. Fat Chio and
He Gong Wei and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins and
Zhihua Wang},
title = {An ultra low power 9-bit 1-MS/s pipelined {SAR} {ADC} for bio-medical
applications},
booktitle = {17th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2010, Athens, Greece, 12-15 December, 2010},
pages = {878--881},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICECS.2010.5724652},
doi = {10.1109/ICECS.2010.5724652},
timestamp = {Fri, 30 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/YinCWSUMW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhuCCSSM10,
author = {Yan Zhu and
Chi{-}Hang Chan and
U. Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A voltage feedback charge compensation technique for split {DAC} architecture
in {SAR} ADCs},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {4061--4064},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537634},
doi = {10.1109/ISCAS.2010.5537634},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhuCCSSM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/MakUM08,
author = {Pui{-}In Mak and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {On the Design of a Programmable-Gain Amplifier With Built-In Compact
DC-Offset Cancellers for Very Low-Voltage {WLAN} Systems},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {55-I},
number = {2},
pages = {496--509},
year = {2008},
url = {https://doi.org/10.1109/TCSI.2007.910643},
doi = {10.1109/TCSI.2007.910643},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/MakUM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/SinCUM08,
author = {Sai{-}Weng Sin and
U{-}Fat Chio and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling
Bandwidth Mismatch},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {55-II},
number = {7},
pages = {648--652},
year = {2008},
url = {https://doi.org/10.1109/TCSII.2008.921600},
doi = {10.1109/TCSII.2008.921600},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/SinCUM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/SinUM08,
author = {Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and
Switched-Opamps},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {55-I},
number = {8},
pages = {2188--2201},
year = {2008},
url = {https://doi.org/10.1109/TCSI.2008.918171},
doi = {10.1109/TCSI.2008.918171},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/SinUM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/DingCWSUM08,
author = {Li Ding and
Sio Chan and
Kim{-}Fai Wong and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo da Silva Martins},
title = {A pseudo-differential comparator-based pipelined {ADC} with common
mode feedforward technique},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
Macao, China, November 30 2008 - December 3, 2008},
pages = {276--279},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/APCCAS.2008.4746013},
doi = {10.1109/APCCAS.2008.4746013},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/DingCWSUM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/KongUM08,
author = {Ngai Kong and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A novel {CMOS} switched-current mode sequential shift forward inference
circuit for fuzzy logic controller},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
Macao, China, November 30 2008 - December 3, 2008},
pages = {396--399},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/APCCAS.2008.4746043},
doi = {10.1109/APCCAS.2008.4746043},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/KongUM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/WongLUM08,
author = {Kim{-}Fai Wong and
Ka{-}Ian Lei and
Seng{-}Pan U and
Rui Paulo da Silva Martins},
title = {A 1-V 90dB {DR} audio stereo {DAC} with embedding headphone driver},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
Macao, China, November 30 2008 - December 3, 2008},
pages = {1160--1163},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/APCCAS.2008.4746231},
doi = {10.1109/APCCAS.2008.4746231},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/WongLUM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/ChioWZSUM08,
author = {U. Fat Chio and
He Gong Wei and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo da Silva Martins},
title = {A self-timing switch-driving register by precharge-evaluate logic
for high-speed {SAR} ADCs},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
Macao, China, November 30 2008 - December 3, 2008},
pages = {1164--1167},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/APCCAS.2008.4746232},
doi = {10.1109/APCCAS.2008.4746232},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/ChioWZSUM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/WeiCZSUM08,
author = {He Gong Wei and
U. Fat Chio and
Yan Zhu and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo da Silva Martins},
title = {A process- and temperature- insensitive current-controlled delay generator
for sampled-data systems},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
Macao, China, November 30 2008 - December 3, 2008},
pages = {1192--1195},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/APCCAS.2008.4746239},
doi = {10.1109/APCCAS.2008.4746239},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/WeiCZSUM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/0001CWSUM08,
author = {Yan Zhu and
U. Fat Chio and
He Gong Wei and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A power-efficient capacitor structure for high-speed charge recycling
{SAR} ADCs},
booktitle = {15th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2008, St. Julien's, Malta, August 31 2008-September
3, 2008},
pages = {642--645},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ICECS.2008.4674935},
doi = {10.1109/ICECS.2008.4674935},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/0001CWSUM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WeiCSUM08,
author = {He Gong Wei and
U. Fat Chio and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A power scalable 6-bit 1.2GS/s flash {ADC} with power on/off Track-and-Hold
and preamplifier},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
pages = {5--8},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISCAS.2008.4541340},
doi = {10.1109/ISCAS.2008.4541340},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/WeiCSUM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/MakUM07,
author = {Pui{-}In Mak and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Experimental 1-V flexible-IF {CMOS} analoguebaseband chain for {IEEE}
802.11a/b/g {WLAN} receivers},
journal = {{IET} Circuits Devices Syst.},
volume = {1},
number = {6},
pages = {415--426},
year = {2007},
url = {https://doi.org/10.1049/iet-cds:20070094},
doi = {10.1049/IET-CDS:20070094},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cds/MakUM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MokMUM07,
author = {Weng{-}leng Mok and
Pui{-}In Mak and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A Highly-Linear Successive-Approximation Front-End Digitizer with
Built-in Sample-and-Hold Function for Pipeline/Two-Step {ADC}},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {1947--1950},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378357},
doi = {10.1109/ISCAS.2007.378357},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/MokMUM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/IeongUM06,
author = {Ka{-}Hou Ao Ieong and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A 1-V 2.5-mW Transient-Improved Current-Steering {DAC} using Charge-Removal-Replacement
Technique},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems 2006, {APCCAS}
2006, Singapore, 4-7 December 2006},
pages = {183--186},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/APCCAS.2006.342362},
doi = {10.1109/APCCAS.2006.342362},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/IeongUM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChioUM06,
author = {Kin{-}Sang Chio and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A dual-mode low-distortion sigma-delta modulator with relaxing comparator
accuracy},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692979},
doi = {10.1109/ISCAS.2006.1692979},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChioUM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LaoUM06,
author = {Chon{-}In Lao and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling
mismatch-free resonator},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692652},
doi = {10.1109/ISCAS.2006.1692652},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LaoUM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MaSUM06,
author = {Jun{-}Xia Ma and
Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash
{ADC} for {UWB} applications},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693581},
doi = {10.1109/ISCAS.2006.1693581},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MaSUM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MakUM06,
author = {Pui{-}In Mak and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {Design and test strategy underlying a low-voltage analog-baseband
{IC} for 802.11a/b/g {WLAN} SiP receivers},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693124},
doi = {10.1109/ISCAS.2006.1693124},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/MakUM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SinUM06,
author = {Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A novel low-voltage finite-gain compensation technique for high-speed
reset- and switched-opamp circuits},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693454},
doi = {10.1109/ISCAS.2006.1693454},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SinUM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/MakUM05,
author = {Pui{-}In Mak and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Two-step channel selection-a novel technique for reconfigurable multistandard
transceiver front-ends},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {52-I},
number = {7},
pages = {1302--1315},
year = {2005},
url = {https://doi.org/10.1109/TCSI.2005.851722},
doi = {10.1109/TCSI.2005.851722},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/MakUM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/MakUM05,
author = {Pui{-}In Mak and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 1-V transient-free and DC-offset-canceled {PGA} with a 17.1-MHz
constant bandwidth over 52-dB control range in 0.35-{\(\mu\)}m {CMOS}},
booktitle = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
{CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
18-21, 2005},
pages = {649--652},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/CICC.2005.1568753},
doi = {10.1109/CICC.2005.1568753},
timestamp = {Tue, 27 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/MakUM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/IeongFMUM05,
author = {Ka{-}Hou Ao Ieong and
Chong{-}Yin Fok and
Pui{-}In Mak and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A frequency up-conversion and two-step channel selection embedded
{CMOS} {D/A} interface},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {392--395},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464607},
doi = {10.1109/ISCAS.2005.1464607},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/IeongFMUM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SinUM05a,
author = {Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A novel very low-voltage {SC-CMFB} technique for fully-differential
reset-opamp circuits},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {1581--1584},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464904},
doi = {10.1109/ISCAS.2005.1464904},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/SinUM05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SinUM05,
author = {Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A novel low-voltage cross-coupled passive sampling branch for reset-
and switched-opamp circuits},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {1585--1588},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464905},
doi = {10.1109/ISCAS.2005.1464905},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/SinUM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LaoUM05,
author = {Chon{-}In Lao and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {3095--3098},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465282},
doi = {10.1109/ISCAS.2005.1465282},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LaoUM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChioUM05,
author = {Kin{-}Sang Chio and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A robust 3rd order low-distortion multi-bit sigma-delta modulator
with reduced number of op-amps for {WCDMA}},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {3099--3102},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465283},
doi = {10.1109/ISCAS.2005.1465283},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChioUM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/UMF04,
author = {Seng{-}Pan U and
Rui Paulo Martins and
Jos{\'{e}} E. Franca},
title = {A 2.5-V 57-MHz 15-tap {SC} bandpass interpolating filter with 320-MS/s
output for {DDFS} system in 0.35-{\(\mu\)} hboxm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {39},
number = {1},
pages = {87--99},
year = {2004},
url = {https://doi.org/10.1109/JSSC.2003.820855},
doi = {10.1109/JSSC.2003.820855},
timestamp = {Wed, 27 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/UMF04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tim/USM04,
author = {Seng{-}Pan U. and
Sai{-}Weng Sin and
Rui Paulo Martins},
title = {Exact spectra analysis of sampled signals with jitter-induced nonuniformly
holding effects},
journal = {{IEEE} Trans. Instrum. Meas.},
volume = {53},
number = {4},
pages = {1279--1288},
year = {2004},
url = {https://doi.org/10.1109/TIM.2004.830787},
doi = {10.1109/TIM.2004.830787},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tim/USM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SinUM04,
author = {Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A generalized timing-skew-free, multi-phase clock generation platform
for parallel sampled-data systems},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {369--372},
publisher = {{IEEE}},
year = {2004},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SinUM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MakUM04,
author = {Pui{-}In Mak and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A low-IF/zero-IF reconfigurable receiver with two-step channel selection
technique for multistandard applications},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {417--420},
publisher = {{IEEE}},
year = {2004},
timestamp = {Fri, 20 May 2016 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MakUM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MakWU04,
author = {Pui{-}In Mak and
Man{-}Chung Wong and
Seng{-}Pan U.},
title = {A 3D {PWM} control, H-bridge tri-level inverter for power quality
compensation in three-phase four-wired systems},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {948--951},
publisher = {{IEEE}},
year = {2004},
timestamp = {Fri, 20 May 2016 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MakWU04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MakMMSHNSM04,
author = {Pui{-}In Mak and
Kin{-}Kwan Ma and
Weng{-}leng Mok and
Chi{-}sam Sou and
Kit{-}man Ho and
Cheng{-}Man Ng and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {An I/Q-multiplexed and OTA-shared {CMOS} pipelined {ADC} with an {A-DQS}
{S/H} front-end for two-step-channel-select low-IF receiver},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {1068--1071},
publisher = {{IEEE}},
year = {2004},
timestamp = {Fri, 20 May 2016 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MakMMSHNSM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/RisquesDAUCCL03,
author = {Jo{\~{a}}o Risques and
Jorge Duarte and
Vasco Amaro and
Seng{-}Pan U and
Kuok Vai Chiang and
Ka Fai Chang and
Keng Chong Lai},
editor = {Jos{\'{e}} E. Franca and
Rudolf Koch},
title = {A very area/power efficient mixed signal circuit for voice signal
processing in 0.18 digital technology},
booktitle = {{ESSCIRC} 2003 - 29th European Solid-State Circuits Conference, Estoril,
Portugal, September 16-18, 2003},
pages = {169--172},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ESSCIRC.2003.1257099},
doi = {10.1109/ESSCIRC.2003.1257099},
timestamp = {Tue, 04 Jul 2023 08:46:31 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/RisquesDAUCCL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/SinUM03,
author = {Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held
signals},
booktitle = {2003 {IEEE} International Conference on Acoustics, Speech, and Signal
Processing, {ICASSP} '03, Hong Kong, April 6-10, 2003},
pages = {253--256},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ICASSP.2003.1201666},
doi = {10.1109/ICASSP.2003.1201666},
timestamp = {Mon, 22 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icassp/SinUM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MakSUM03,
author = {Pui{-}In Mak and
Chi{-}sam Sou and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Frequency-downconversion and {IF} channel selection {A-DQS} sample-and-hold
pair for two-step-channel-select low-IF receiver},
booktitle = {Proceedings of the 2003 10th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2003, Sharjah, United Arab Emirates,
December 14-17, 2003},
pages = {479--482},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ICECS.2003.1301826},
doi = {10.1109/ICECS.2003.1301826},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/MakSUM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MakUM03,
author = {Pui{-}In Mak and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A front-to-back-end modeling of {I/Q} mismatch effects in a complex-IF
receiver for image-rejection enhancement},
booktitle = {Proceedings of the 2003 10th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2003, Sharjah, United Arab Emirates,
December 14-17, 2003},
pages = {631--634},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ICECS.2003.1301864},
doi = {10.1109/ICECS.2003.1301864},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/MakUM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SinSMJF03,
author = {Sai{-}Weng Sin and
Seng{-}Pan U. and
Rui Paulo Martins and
Jos{\'{e}} E. Franca},
title = {Timing-mismatch analysis in high-speed analog front-end with nonuniformly
holding output},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {129--132},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1205517},
doi = {10.1109/ISCAS.2003.1205517},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SinSMJF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LaoLAMUM03,
author = {Chon{-}In Lao and
Ho{-}leng Leong and
Kuoi{-}Fok Au and
Kuok{-}Hang Mok and
Seng{-}Pan U. and
Rui Paulo Martins},
title = {A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp
{SC} resonator with double-sampling},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {1061--1064},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1205750},
doi = {10.1109/ISCAS.2003.1205750},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LaoLAMUM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/LouUM02,
author = {Fan Lou and
Seng{-}Pan U and
Rui Paulo Martins},
title = {N-path multirate sigma-delta modulator for high-frequency applications},
booktitle = {Proceedings of the 2002 9th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2002, Dubrovnik, Croatia, September
15-18, 2002},
pages = {315--318},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ICECS.2002.1045397},
doi = {10.1109/ICECS.2002.1045397},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/LouUM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF02,
author = {Seng{-}Pan U. and
Rui Paulo Martins and
Jos{\'{e}} E. Franca},
title = {Design and analysis of low timing-skew clock generation for time-interleaved
sampled-data systems},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {441--444},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1010486},
doi = {10.1109/ISCAS.2002.1010486},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/UMF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF01,
author = {Seng{-}Pan U. and
Rui Paulo Martins and
Jos{\'{e}} E. Franca},
title = {High-frequency low-power multirate {SC} realizations for {NTSC/PAL}
digital video filtering},
booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems,
{ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
pages = {204--207},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ISCAS.2001.921826},
doi = {10.1109/ISCAS.2001.921826},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/UMF01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF01a,
author = {Seng{-}Pan U. and
Rui Paulo Martins and
Jos{\'{e}} E. Franca},
title = {A high-speed frequency up-translated {SC} bandpass filter with auto-zeroing
for {DDFS} systems},
booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems,
{ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
pages = {320--323},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ISCAS.2001.921857},
doi = {10.1109/ISCAS.2001.921857},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/UMF01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF00,
author = {Seng{-}Pan U and
Rui Paulo Martins and
Jos{\'{e}} E. Franca},
title = {A linear-phase halfband {SC} video interpolation filter with coefficient-sharing
and spread-reduction},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {177--180},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.856025},
doi = {10.1109/ISCAS.2000.856025},
timestamp = {Fri, 13 Aug 2021 09:26:01 +0200},
biburl = {https://dblp.org/rec/conf/iscas/UMF00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF99,
author = {Seng{-}Pan U. and
Rui Paulo Martins and
Jos{\'{e}} E. Franca},
title = {Highly accurate mismatch-free {SC} delay circuits with reduced finite
gain and offset sensitivity},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {57--60},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.780618},
doi = {10.1109/ISCAS.1999.780618},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/UMF99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF99a,
author = {Seng{-}Pan U. and
Rui Paulo Martins and
Jos{\'{e}} E. Franca},
title = {High performance multirate {SC} circuits with predictive correlated
double sampling technique},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {77--80},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.780623},
doi = {10.1109/ISCAS.1999.780623},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/UMF99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/UMF98,
author = {Seng{-}Pan U and
Rui Paulo Martins and
Jos{\'{e}} E. Franca},
title = {A novel half-band {SC} architecture for efficient analog impulse sampled
interpolation},
booktitle = {5th {IEEE} International Conference on Electronics, Circuits and Systems,
{ICECS} 1998, Surfing the Waves of Science and Technology, Lisbon,
Portugal, September 7-10, 1998},
pages = {389--393},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/ICECS.1998.813347},
doi = {10.1109/ICECS.1998.813347},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/UMF98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/UMF96,
author = {Seng{-}Pan U. and
Rui Paulo Martins and
Jos{\'{e}} E. Franca},
title = {New impulse sampled {IIR} switched-capacitor interpolators},
booktitle = {Proceedings of Third International Conference on Electronics, Circuits,
and Systems, {ICECS} 1996, Rodos, Greece, October 13-16, 1996},
pages = {203--206},
publisher = {{IEEE}},
year = {1996},
url = {https://doi.org/10.1109/ICECS.1996.582778},
doi = {10.1109/ICECS.1996.582778},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/UMF96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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