BibTeX records: Luyen Vu

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@inproceedings{DBLP:conf/isscc/PeknyVTSYPXDCPX22,
  author       = {Ted Pekny and
                  Luyen Vu and
                  Jeff Tsai and
                  Dheeraj Srinivasan and
                  Erwin Yu and
                  Jonathan Pabustan and
                  Joe Xu and
                  Srinivas Deshmukh and
                  Kim{-}Fung Chan and
                  Michael Piccardi and
                  Kevin Xu and
                  Guan Wang and
                  Kaveh Shakeri and
                  Vipul Patel and
                  Tomoko Iwasaki and
                  Tongji Wang and
                  Padma Musunuri and
                  Carl Gu and
                  Ali Mohammadzadeh and
                  Ali Ghalam and
                  Violante Moschiano and
                  Tommaso Vali and
                  Jae{-}Kwan Park and
                  June Lee and
                  Ramin Ghodsi},
  title        = {A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent
                  Planes for Read using CMOS-Under-the-Array},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
                  San Francisco, CA, USA, February 20-26, 2022},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/ISSCC42614.2022.9731691},
  doi          = {10.1109/ISSCC42614.2022.9731691},
  timestamp    = {Tue, 16 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/PeknyVTSYPXDCPX22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/TanakaHVGKPYPEG16,
  author       = {Tomoharu Tanaka and
                  Mark Helm and
                  Tommaso Vali and
                  Ramin Ghodsi and
                  Koichi Kawai and
                  Jae{-}Kwan Park and
                  Shigekazu Yamada and
                  Feng Pan and
                  Yuichi Einaga and
                  Ali Ghalam and
                  Toru Tanzawa and
                  Jason Guo and
                  Takaaki Ichikawa and
                  Erwin Yu and
                  Satoru Tamada and
                  Tetsuji Manabe and
                  Jiro Kishimoto and
                  Yoko Oikawa and
                  Yasuhiro Takashima and
                  Hidehiko Kuge and
                  Midori Morooka and
                  Ali Mohammadzadeh and
                  Jong Kang and
                  Jeff Tsai and
                  Emanuele Sirizotti and
                  Eric Lee and
                  Luyen Vu and
                  Yuxing Liu and
                  Hoon Choi and
                  Kwonsu Cheon and
                  Daesik Song and
                  Daniel Shin and
                  Jung Hee Yun and
                  Michele Piccardi and
                  Kim{-}Fung Chan and
                  Yogesh Luthra and
                  Dheeraj Srinivasan and
                  Srinivasarao Deshmukh and
                  Kalyan Kavalipurapu and
                  Dan Nguyen and
                  Girolamo Gallo and
                  Sumant Ramprasad and
                  Michelle Luo and
                  Qiang Tang and
                  Michele Incarnati and
                  Agostino Macerola and
                  Luigi Pilolli and
                  Luca De Santis and
                  Massimo Rossini and
                  Violante Moschiano and
                  Giovanni Santin and
                  Bernardino Tronca and
                  Hyunseok Lee and
                  Vipul Patel and
                  Ted Pekny and
                  Aaron Yip and
                  Naveen Prabhu and
                  Purval Sule and
                  Trupti Bemalkhedkar and
                  Kiranmayee Upadhyayula and
                  Camila Jaramillo},
  title        = {7.7 {A} 768Gb 3b/cell 3D-floating-gate {NAND} flash memory},
  booktitle    = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  pages        = {142--144},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISSCC.2016.7417947},
  doi          = {10.1109/ISSCC.2016.7417947},
  timestamp    = {Tue, 16 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/TanakaHVGKPYPEG16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/HelmPGGHHKKLMNP14,
  author       = {Mark Helm and
                  Jae{-}Kwan Park and
                  Ali Ghalam and
                  Jason Guo and
                  Chang{-}Wan Ha and
                  Cairong Hu and
                  Heonwook Kim and
                  Kalyan Kavalipurapu and
                  Eric Lee and
                  Ali Mohammadzadeh and
                  Dan Nguyen and
                  Vipul Patel and
                  Ted Pekny and
                  Bill Saiki and
                  Daesik Song and
                  Jeff Tsai and
                  Vimon Viajedor and
                  Luyen Vu and
                  Tinwai Wong and
                  Jung Hee Yun and
                  Ramin Ghodsi and
                  Andrea D'Alessandro and
                  Domenico Di Cicco and
                  Violante Moschiano},
  title        = {19.1 {A} 128Gb {MLC} NAND-Flash device using 16nm planar cell},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {326--327},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757454},
  doi          = {10.1109/ISSCC.2014.6757454},
  timestamp    = {Tue, 16 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/HelmPGGHHKKLMNP14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/NobunagaARLYVATSRVCCBVMCULQTJLM08,
  author       = {Dean Nobunaga and
                  Ebrahim Abedifard and
                  Frankie Roohparvar and
                  June Lee and
                  Erwin Yu and
                  Allahyar Vahidimowlavi and
                  Michael Abraham and
                  Sanjay Talreja and
                  Rajesh Sundaram and
                  Rod Rozman and
                  Luyen Vu and
                  Chih{-}Liang Chen and
                  Uday Chandrasekhar and
                  Rupinder Bains and
                  Vimon Viajedor and
                  William Mak and
                  Munseork Choi and
                  Darshak Udeshi and
                  Michelle Luo and
                  Shahid Qureshi and
                  Jeffrey Tsai and
                  Frederick Jaffin and
                  Yujiang Liu and
                  Marco Mancinelli},
  title        = {A 50nm 8Gb {NAND} Flash Memory with 100MB/s Program Throughput and
                  200MB/s {DDR} Interface},
  booktitle    = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2008, Digest of Technical Papers, San Francisco, CA, USA, February
                  3-7, 2008},
  pages        = {426--527},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISSCC.2008.4523239},
  doi          = {10.1109/ISSCC.2008.4523239},
  timestamp    = {Tue, 16 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/NobunagaARLYVATSRVCCBVMCULQTJLM08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}