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ORCIDBibTeX records: Chia-Lin Yang
@article{DBLP:journals/computer/Yang23,
author = {Chia{-}Lin Yang},
title = {Understanding Computer Architecture Sustainability},
journal = {Computer},
volume = {56},
number = {9},
pages = {4--5},
year = {2023},
url = {https://doi.org/10.1109/MC.2023.3290271},
doi = {10.1109/MC.2023.3290271},
timestamp = {Thu, 31 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/Yang23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/WeiYHCAY23,
author = {Ming{-}Liang Wei and
Mikail Yayla and
Shu{-}Yin Ho and
Jian{-}Jia Chen and
Hussam Amrouch and
Chia{-}Lin Yang},
title = {Impact of Non-Volatile Memory Cells on Spiking Neural Network Annealing
Machine With In-Situ Synapse Processing},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {70},
number = {11},
pages = {4380--4393},
year = {2023},
url = {https://doi.org/10.1109/TCSI.2023.3305010},
doi = {10.1109/TCSI.2023.3305010},
timestamp = {Thu, 09 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcasI/WeiYHCAY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/HenkelSBTWTMCKFLCHCYC23,
author = {J{\"{o}}rg Henkel and
Lokesh Siddhu and
Lars Bauer and
J{\"{u}}rgen Teich and
Stefan Wildermann and
Mehdi B. Tahoori and
Mahta Mayahinia and
Jer{\'{o}}nimo Castrill{\'{o}}n and
Asif Ali Khan and
Hamid Farzaneh and
Jo{\~{a}}o Paulo C. de Lima and
Jian{-}Jia Chen and
Christian Hakert and
Kuan{-}Hsun Chen and
Chia{-}Lin Yang and
Hsiang{-}Yun Cheng},
editor = {Jana Doppa and
Swarup Bhunia},
title = {Special Session - Non-Volatile Memories: Challenges and Opportunities
for Embedded System Architectures with Focus on Machine Learning Applications},
booktitle = {International Conference on Compilers, Architecture, and Synthesis
for Embedded Systems, {CASES} 2023, Hamburg, Germany, September 17-22,
2023},
pages = {11--20},
publisher = {{ACM/IEEE}},
year = {2023},
url = {https://doi.org/10.1145/3607889.3609088},
doi = {10.1145/3607889.3609088},
timestamp = {Sat, 10 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/HenkelSBTWTMCKFLCHCYC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChenKY23,
author = {Xuan{-}Jun Chen and
Cynthia Kuan and
Chia{-}Lin Yang},
title = {Unified Agile Accuracy Assessment in Computing-in-Memory Neural Accelerators
by Layerwise Dynamical Isometry},
booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco,
CA, USA, July 9-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DAC56929.2023.10247782},
doi = {10.1109/DAC56929.2023.10247782},
timestamp = {Sun, 24 Sep 2023 13:31:06 +0200},
biburl = {https://dblp.org/rec/conf/dac/ChenKY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/LinCCY23,
author = {Shao{-}Fu Lin and
Yi{-}Jung Chen and
Hsiang{-}Yun Cheng and
Chia{-}Lin Yang},
title = {Tensor Movement Orchestration in Multi-GPU Training Systems},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2023, Montreal, QC, Canada, February 25 - March 1, 2023},
pages = {1140--1152},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/HPCA56546.2023.10071043},
doi = {10.1109/HPCA56546.2023.10071043},
timestamp = {Wed, 29 Mar 2023 11:07:46 +0200},
biburl = {https://dblp.org/rec/conf/hpca/LinCCY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/YaylaTIWHAYCA23,
author = {Mikail Yayla and
Simon Thomann and
Md. Mazharul Islam and
Ming{-}Liang Wei and
Shu{-}Yin Ho and
Ahmedullah Aziz and
Chia{-}Lin Yang and
Jian{-}Jia Chen and
Hussam Amrouch},
title = {Reliable Brain-inspired {AI} Accelerators using Classical and Emerging
Memories},
booktitle = {41st {IEEE} {VLSI} Test Symposium, {VTS} 2023, San Diego, CA, USA,
April 24-26, 2023},
pages = {1--10},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VTS56346.2023.10140068},
doi = {10.1109/VTS56346.2023.10140068},
timestamp = {Fri, 26 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/YaylaTIWHAYCA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2309-02111,
author = {Mikail Yayla and
Simon Thomann and
Ming{-}Liang Wei and
Chia{-}Lin Yang and
Jian{-}Jia Chen and
Hussam Amrouch},
title = {{HW/SW} Codesign for Robust and Efficient Binarized SNNs by Capacitor
Minimization},
journal = {CoRR},
volume = {abs/2309.02111},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2309.02111},
doi = {10.48550/ARXIV.2309.02111},
eprinttype = {arXiv},
eprint = {2309.02111},
timestamp = {Mon, 11 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2309-02111.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/Yang22,
author = {Chia{-}Lin Yang},
title = {A Forward Speculative Interference Attack},
journal = {Computer},
volume = {55},
number = {6},
pages = {4--5},
year = {2022},
url = {https://doi.org/10.1109/MC.2022.3164223},
doi = {10.1109/MC.2022.3164223},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/Yang22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/LinCYLLHCLCTN22,
author = {Wei{-}Ting Lin and
Hsiang{-}Yun Cheng and
Chia{-}Lin Yang and
Meng{-}Yao Lin and
Kai Lien and
Han{-}Wen Hu and
Hung{-}Sheng Chang and
Hsiang{-}Pang Li and
Meng{-}Fan Chang and
Yen{-}Ting Tsou and
Chin{-}Fu Nien},
title = {{DL-RSIM:} {A} Reliability and Deployment Strategy Simulation Framework
for ReRAM-based {CNN} Accelerators},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {21},
number = {3},
pages = {24:1--24:29},
year = {2022},
url = {https://doi.org/10.1145/3507639},
doi = {10.1145/3507639},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/LinCYLLHCLCTN22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LinLCJY22,
author = {Chung{-}Hsiang Lin and
Shao{-}Fu Lin and
Yi{-}Jung Chen and
En{-}Yu Jenp and
Chia{-}Lin Yang},
title = {{PUMP:} Profiling-free Unified Memory Prefetcher for Large {DNN} Model
Support},
booktitle = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2022, Taipei, Taiwan, January 17-20, 2022},
pages = {122--127},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASP-DAC52403.2022.9712507},
doi = {10.1109/ASP-DAC52403.2022.9712507},
timestamp = {Fri, 04 Mar 2022 13:11:07 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LinLCJY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/TsouCYCCT22,
author = {Yen{-}Ting Tsou and
Kuan{-}Hsun Chen and
Chia{-}Lin Yang and
Hsiang{-}Yun Cheng and
Jian{-}Jia Chen and
Der{-}Yu Tsai},
title = {This is SPATEM! {A} Spatial-Temporal Optimization Framework for Efficient
Inference on ReRAM-based {CNN} Accelerator},
booktitle = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2022, Taipei, Taiwan, January 17-20, 2022},
pages = {702--707},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASP-DAC52403.2022.9712536},
doi = {10.1109/ASP-DAC52403.2022.9712536},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/TsouCYCCT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/YenHCCYCL22,
author = {Jui{-}Nan Yen and
Yao{-}Ching Hsieh and
Cheng{-}Yu Chen and
Tseng{-}Yi Chen and
Chia{-}Lin Yang and
Hsiang{-}Yun Cheng and
Yixin Luo},
title = {Efficient Bad Block Management with Cluster Similarity},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2022, Seoul, South Korea, April 2-6, 2022},
pages = {503--513},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/HPCA53966.2022.00044},
doi = {10.1109/HPCA53966.2022.00044},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/YenHCCYCL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/SunWLYKX22,
author = {Xuan Sun and
Hu Wan and
Qiao Li and
Chia{-}Lin Yang and
Tei{-}Wei Kuo and
Chun Jason Xue},
title = {{RM-SSD:} In-Storage Computing for Large-Scale Recommendation Inference},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2022, Seoul, South Korea, April 2-6, 2022},
pages = {1056--1070},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/HPCA53966.2022.00081},
doi = {10.1109/HPCA53966.2022.00081},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/SunWLYKX22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nvmsa/DongCYLL22,
author = {Nai{-}Jia Dong and
Hsiang{-}Yun Cheng and
Chia{-}Lin Yang and
Bo{-}Rong Lin and
Hsiang{-}Pang Li},
title = {Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid
Logging},
booktitle = {11th {IEEE} Non-Volatile Memory Systems and Applications Symposium,
{NVMSA} 2022, Taipei, Taiwan, August 23-25, 2022},
pages = {1--7},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/NVMSA56066.2022.00010},
doi = {10.1109/NVMSA56066.2022.00010},
timestamp = {Wed, 05 Oct 2022 15:16:45 +0200},
biburl = {https://dblp.org/rec/conf/nvmsa/DongCYLL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/bioinformatics/LinHTCHYLC21,
author = {Jun{-}Liang Lin and
Tsung{-}Ting Hsieh and
Yi{-}An Tung and
Xuan{-}Jun Chen and
Yu{-}Chun Hsiao and
Chia{-}Lin Yang and
Tyng{-}Luh Liu and
Chien{-}Yu Chen},
title = {ezGeno: an automatic model selection package for genomic data analysis},
journal = {Bioinform.},
volume = {38},
number = {1},
pages = {30--37},
year = {2021},
url = {https://doi.org/10.1093/bioinformatics/btab588},
doi = {10.1093/BIOINFORMATICS/BTAB588},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/bioinformatics/LinHTCHYLC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apsys/00010CYKX21,
author = {Hu Wan and
Xuan Sun and
Yufei Cui and
Chia{-}Lin Yang and
Tei{-}Wei Kuo and
Chun Jason Xue},
editor = {Haryadi S. Gunawi and
Xiaosong Ma},
title = {FlashEmbedding: storing embedding tables in {SSD} for large-scale
recommender systems},
booktitle = {APSys '21: 12th {ACM} {SIGOPS} Asia-Pacific Workshop on Systems, Hong
Kong, China, August 24-25, 2021},
pages = {9--16},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3476886.3477511},
doi = {10.1145/3476886.3477511},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apsys/00010CYKX21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChengWHC0CYK21,
author = {Hsiang{-}Yun Cheng and
Chun{-}Feng Wu and
Christian Hakert and
Kuan{-}Hsun Chen and
Yuan{-}Hao Chang and
Jian{-}Jia Chen and
Chia{-}Lin Yang and
Tei{-}Wei Kuo},
title = {Future Computing Platform Design: {A} Cross-Layer Design Approach},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {312--317},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474229},
doi = {10.23919/DATE51398.2021.9474229},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/ChengWHC0CYK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WeiYHCYA21,
author = {Ming{-}Liang Wei and
Mikail Yayla and
Shu{-}Yin Ho and
Jian{-}Jia Chen and
Chia{-}Lin Yang and
Hussam Amrouch},
title = {Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks
through Binarization},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--9},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643463},
doi = {10.1109/ICCAD51958.2021.9643463},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/WeiYHCYA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irps/WeiASLYWL21,
author = {Ming{-}Liang Wei and
Hussam Amrouch and
Cheng{-}Lin Sung and
Hang{-}Ting Lue and
Chia{-}Lin Yang and
Keh{-}Chung Wang and
Chih{-}Yuan Lu},
title = {Robust Brain-Inspired Computing: On the Reliability of Spiking Neural
Network Using Emerging Non-Volatile Synapses},
booktitle = {{IEEE} International Reliability Physics Symposium, {IRPS} 2021, Monterey,
CA, USA, March 21-25, 2021},
pages = {1--8},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/IRPS46558.2021.9405141},
doi = {10.1109/IRPS46558.2021.9405141},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/irps/WeiASLYWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LinCYC21,
author = {Yu{-}Sheng Lin and
Wei{-}Chao Chen and
Chia{-}Lin Yang and
Shao{-}Yi Chien},
title = {A Dense Tensor Accelerator with Data Exchange Mesh for {DNN} and Vision
Workloads},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401421},
doi = {10.1109/ISCAS51556.2021.9401421},
timestamp = {Fri, 02 Jul 2021 12:26:54 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LinCYC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/KeCYH21,
author = {Zhi{-}Lin Ke and
Hsiang{-}Yun Cheng and
Chia{-}Lin Yang and
Han{-}Wei Huang},
title = {Analyzing the Interplay Between Random Shuffling and Storage Devices
for Efficient Machine Learning},
booktitle = {{IEEE} International Symposium on Performance Analysis of Systems
and Software, {ISPASS} 2021, Stony Brook, NY, USA, March 28-30, 2021},
pages = {276--287},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISPASS51385.2021.00050},
doi = {10.1109/ISPASS51385.2021.00050},
timestamp = {Wed, 05 May 2021 09:46:27 +0200},
biburl = {https://dblp.org/rec/conf/ispass/KeCYH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2111-12885,
author = {Yu{-}Sheng Lin and
Wei{-}Chao Chen and
Chia{-}Lin Yang and
Shao{-}Yi Chien},
title = {A Dense Tensor Accelerator with Data Exchange Mesh for {DNN} and Vision
Workloads},
journal = {CoRR},
volume = {abs/2111.12885},
year = {2021},
url = {https://arxiv.org/abs/2111.12885},
eprinttype = {arXiv},
eprint = {2111.12885},
timestamp = {Wed, 01 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2111-12885.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhengWFYCHCYL20,
author = {Qilin Zheng and
Zongwei Wang and
Zishun Feng and
Bonan Yan and
Yimao Cai and
Ru Huang and
Yiran Chen and
Chia{-}Lin Yang and
Hai Helen Li},
title = {Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture
for Accelerating Deep Convolution Neural Networks},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218590},
doi = {10.1109/DAC18072.2020.9218590},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/ZhengWFYCHCYL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HenkelARSRGYNZH19,
author = {J{\"{o}}rg Henkel and
Hussam Amrouch and
Martin Rapp and
Sami Salamin and
Dayane Reis and
Di Gao and
Xunzhao Yin and
Michael T. Niemier and
Cheng Zhuo and
Xiaobo Sharon Hu and
Hsiang{-}Yun Cheng and
Chia{-}Lin Yang},
editor = {David Z. Pan},
title = {The Impact of Emerging Technologies on Architectures and System-level
Management: Invited Paper},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2019, Westminster, CO, USA, November 4-7, 2019},
pages = {1--6},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1109/ICCAD45719.2019.8942102},
doi = {10.1109/ICCAD45719.2019.8942102},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HenkelARSRGYNZH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icip/LeeLYC19,
author = {Chien{-}I Lee and
Meng{-}Yao Lin and
Chia{-}Lin Yang and
Yen{-}Kuang Chen},
title = {Iotbench: {A} Benchmark Suite for Intelligent Internet of Things Edge
Devices},
booktitle = {2019 {IEEE} International Conference on Image Processing, {ICIP} 2019,
Taipei, Taiwan, September 22-25, 2019},
pages = {170--174},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICIP.2019.8802949},
doi = {10.1109/ICIP.2019.8802949},
timestamp = {Wed, 11 Dec 2019 16:30:23 +0100},
biburl = {https://dblp.org/rec/conf/icip/LeeLYC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/YangCYTHCL19,
author = {Tzu{-}Hsien Yang and
Hsiang{-}Yun Cheng and
Chia{-}Lin Yang and
I{-}Ching Tseng and
Han{-}Wen Hu and
Hung{-}Sheng Chang and
Hsiang{-}Pang Li},
editor = {Srilatha Bobbie Manne and
Hillery C. Hunter and
Erik R. Altman},
title = {Sparse ReRAM engine: joint exploration of activation and weight sparsity
in compressed neural networks},
booktitle = {Proceedings of the 46th International Symposium on Computer Architecture,
{ISCA} 2019, Phoenix, AZ, USA, June 22-26, 2019},
pages = {236--249},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3307650.3322271},
doi = {10.1145/3307650.3322271},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/YangCYTHCL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nvmsa/JiWLGSYX19,
author = {Cheng Ji and
Lun Wang and
Qiao Li and
Congming Gao and
Liang Shi and
Chia{-}Lin Yang and
Chun Jason Xue},
title = {Fair Down to the Device: {A} GC-Aware Fair Scheduler for {SSD}},
booktitle = {2019 {IEEE} Non-Volatile Memory Systems and Applications Symposium,
{NVMSA} 2019, Hangzhou, China, August 18-21, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/NVMSA.2019.8863523},
doi = {10.1109/NVMSA.2019.8863523},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/nvmsa/JiWLGSYX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/FuWY18,
author = {Hsueh{-}Chun Fu and
Po{-}Han Wang and
Chia{-}Lin Yang},
title = {Active forwarding: eliminate {IOMMU} address translation for accelerator-rich
architectures},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {112:1--112:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3195984},
doi = {10.1145/3195970.3195984},
timestamp = {Tue, 04 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/FuWY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LinCLYTYHCLC18,
author = {Meng{-}Yao Lin and
Hsiang{-}Yun Cheng and
Wei{-}Ting Lin and
Tzu{-}Hsien Yang and
I{-}Ching Tseng and
Chia{-}Lin Yang and
Han{-}Wen Hu and
Hung{-}Sheng Chang and
Hsiang{-}Pang Li and
Meng{-}Fan Chang},
editor = {Iris Bahar},
title = {{DL-RSIM:} a simulation framework to enable reliable ReRAM-based accelerators
for deep learning},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {31},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240800},
doi = {10.1145/3240765.3240800},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LinCLYTYHCLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1810-04509,
author = {Zhi{-}Lin Ke and
Hsiang{-}Yun Cheng and
Chia{-}Lin Yang},
title = {{LIRS:} Enabling efficient machine learning on NVM-based storage via
a lightweight implementation of random shuffling},
journal = {CoRR},
volume = {abs/1810.04509},
year = {2018},
url = {http://arxiv.org/abs/1810.04509},
eprinttype = {arXiv},
eprint = {1810.04509},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1810-04509.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/ChenCWY17,
author = {Li{-}Jhan Chen and
Hsiang{-}Yun Cheng and
Po{-}Han Wang and
Chia{-}Lin Yang},
title = {Improving {GPGPU} Performance via Cache Locality Aware Thread Block
Scheduling},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {16},
number = {2},
pages = {127--131},
year = {2017},
url = {https://doi.org/10.1109/LCA.2017.2693371},
doi = {10.1109/LCA.2017.2693371},
timestamp = {Tue, 04 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cal/ChenCWY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/GarrettY17,
author = {David Garrett and
Chia{-}Lin Yang},
title = {Recap of the 2017 International Symposium on Low Power Electronics
and Design {(ISLPED)}},
journal = {{IEEE} Des. Test},
volume = {34},
number = {6},
pages = {121--122},
year = {2017},
url = {https://doi.org/10.1109/MDAT.2017.2746561},
doi = {10.1109/MDAT.2017.2746561},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/GarrettY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ChangCCYECY17,
author = {Che{-}Wei Chang and
Geng{-}You Chen and
Yi{-}Jung Chen and
Chia{-}Wei Yeh and
Pei Yin Eng and
Ana Cheung and
Chia{-}Lin Yang},
title = {Exploiting Write Heterogeneity of Morphable {MLC/SLC} SSDs in Datacenters
with Service-Level Objectives},
journal = {{IEEE} Trans. Computers},
volume = {66},
number = {8},
pages = {1457--1463},
year = {2017},
url = {https://doi.org/10.1109/TC.2017.2677425},
doi = {10.1109/TC.2017.2677425},
timestamp = {Tue, 18 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/ChangCCYECY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LinYLW17,
author = {Ye{-}Jyun Lin and
Chia{-}Lin Yang and
Hsiang{-}Pang Li and
Cheng{-}Yuan Michael Wang},
title = {A Hybrid {DRAM/PCM} Buffer Cache Architecture for Smartphones with
QoS Consideration},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {22},
number = {2},
pages = {27:1--27:22},
year = {2017},
url = {https://doi.org/10.1145/2979143},
doi = {10.1145/2979143},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LinYLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ShiehCFWY17,
author = {Li{-}Wei Shieh and
Kun{-}Chih Chen and
Hsueh{-}Chun Fu and
Po{-}Han Wang and
Chia{-}Lin Yang},
title = {Enabling fast preemption via Dual-Kernel support on GPUs},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {121--126},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858307},
doi = {10.1109/ASPDAC.2017.7858307},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ShiehCFWY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LaiZY17,
author = {Chun{-}Hao Lai and
Jishen Zhao and
Chia{-}Lin Yang},
title = {Leave the Cache Hierarchy Operation as It Is: {A} New Persistent Memory
Accelerating Approach},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {5:1--5:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062272},
doi = {10.1145/3061639.3062272},
timestamp = {Tue, 06 Nov 2018 16:58:15 +0100},
biburl = {https://dblp.org/rec/conf/dac/LaiZY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/GarrettY17,
author = {David Garrett and
Chia{-}Lin Yang},
title = {Message from the general co-chairs},
booktitle = {2017 {IEEE/ACM} International Symposium on Low Power Electronics and
Design, {ISLPED} 2017, Taipei, Taiwan, July 24-26, 2017},
pages = {1},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISLPED.2017.8009140},
doi = {10.1109/ISLPED.2017.8009140},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/GarrettY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/WangTWCWCLSYHKL17,
author = {Li Wang and
Ren{-}Wei Tsai and
Shao{-}Chung Wang and
Kun{-}Chih Chen and
Po{-}Han Wang and
Hsiang{-}Yun Cheng and
Yi{-}Chung Lee and
Sheng{-}Jie Shu and
Chun{-}Chieh Yang and
Min{-}Yih Hsu and
Li{-}Chen Kan and
Chao{-}Lin Lee and
Tzu{-}Chieh Yu and
Rih{-}Ding Peng and
Chia{-}Lin Yang and
Yuan{-}Shin Hwang and
Jenq Kuen Lee and
Shiao{-}Li Tsao and
Ming Ouhyoung},
title = {Analyzing OpenCL 2.0 workloads using a heterogeneous {CPU-GPU} simulator},
booktitle = {2017 {IEEE} International Symposium on Performance Analysis of Systems
and Software, {ISPASS} 2017, Santa Rosa, CA, USA, April 24-25, 2017},
pages = {127--128},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISPASS.2017.7975279},
doi = {10.1109/ISPASS.2017.7975279},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispass/WangTWCWCLSYHKL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/LiuCYLHL16,
author = {Ren{-}Shuo Liu and
Meng{-}Yen Chuang and
Chia{-}Lin Yang and
Cheng{-}Hsuan Li and
Kin{-}Chu Ho and
Hsiang{-}Pang Li},
title = {Improving Read Performance of {NAND} Flash SSDs by Exploiting Error
Locality},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {4},
pages = {1090--1102},
year = {2016},
url = {https://doi.org/10.1109/TC.2014.2345387},
doi = {10.1109/TC.2014.2345387},
timestamp = {Thu, 08 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/LiuCYLHL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChenSYL16,
author = {Renhai Chen and
Zili Shao and
Chia{-}Lin Yang and
Tao Li},
title = {MCSSim: {A} memory channel storage simulator},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {153--158},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428004},
doi = {10.1109/ASPDAC.2016.7428004},
timestamp = {Wed, 15 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChenSYL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WangLY16,
author = {Po{-}Han Wang and
Cheng{-}Hsuan Li and
Chia{-}Lin Yang},
title = {Latency sensitivity-based cache partitioning for heterogeneous multi-core
architecture},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {5:1--5:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898036},
doi = {10.1145/2897937.2898036},
timestamp = {Tue, 04 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WangLY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/LinSCYW15,
author = {Chung{-}Hsiang Lin and
De{-}Yu Shen and
Yi{-}Jung Chen and
Chia{-}Lin Yang and
Cheng{-}Yuan Michael Wang},
title = {{SECRET:} {A} Selective Error Correction Framework for Refresh Energy
Reduction in DRAMs},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {12},
number = {2},
pages = {19:19:1--19:19:24},
year = {2015},
url = {https://doi.org/10.1145/2747876},
doi = {10.1145/2747876},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/LinSCYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/LinYHLHC15,
author = {Ye{-}Jyun Lin and
Chia{-}Lin Yang and
Jiao{-}Wei Huang and
Tay{-}Jyi Lin and
Chih{-}Wen Hsueh and
Naehyuck Chang},
title = {System-Level Performance and Power Optimization for MPSoC: {A} Memory
Access-Aware Approach},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {14},
number = {1},
pages = {8:1--8:26},
year = {2015},
url = {https://doi.org/10.1145/2656339},
doi = {10.1145/2656339},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/LinYHLHC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/LaiYYL15,
author = {Chun{-}Hao Lai and
Shun{-}Chih Yu and
Chia{-}Lin Yang and
Hsiang{-}Pang Li},
title = {Fine-grained write scheduling for {PCM} performance improvement under
write power budget},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2015, Rome, Italy, July 22-24, 2015},
pages = {19--24},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISLPED.2015.7273484},
doi = {10.1109/ISLPED.2015.7273484},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/LaiYYL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/LuLY15,
author = {Shih{-}Lien Lu and
Ying{-}Chen Lin and
Chia{-}Lin Yang},
editor = {Milos Prvulovic},
title = {Improving {DRAM} latency with dynamic asymmetric subarray},
booktitle = {Proceedings of the 48th International Symposium on Microarchitecture,
{MICRO} 2015, Waikiki, HI, USA, December 5-9, 2015},
pages = {255--266},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2830772.2830827},
doi = {10.1145/2830772.2830827},
timestamp = {Wed, 11 Aug 2021 11:51:26 +0200},
biburl = {https://dblp.org/rec/conf/micro/LuLY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nvmsa/LinYLW15,
author = {Ye{-}Jyun Lin and
Chia{-}Lin Yang and
Hsiang{-}Pang Li and
Cheng{-}Yuan Michael Wang},
title = {A buffer cache architecture for smartphones with hybrid {DRAM/PCM}
memory},
booktitle = {{IEEE} Non-Volatile Memory System and Applications Symposium, {NVMSA}
2015, Hong Kong, China, August 19-21, 2015},
pages = {1--6},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/NVMSA.2015.7304363},
doi = {10.1109/NVMSA.2015.7304363},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/nvmsa/LinYLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/racs/ChenYLL15,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Ping{-}Sheng Lin and
Yi{-}Chang Lu},
editor = {Esmaeil S. Nadimi and
Tom{\'{a}}s Cern{\'{y}} and
Sung{-}Ryul Kim and
Wei Wang},
title = {Thermal/performance characterization of CMPs with 3D-stacked DRAMs
under synergistic voltage-frequency control of cores and DRAMs},
booktitle = {Proceedings of the 2015 Conference on research in adaptive and convergent
systems, {RACS} 2015, Prague, Czech Republic, October 9-12, 2015},
pages = {430--436},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2811411.2811515},
doi = {10.1145/2811411.2811515},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/racs/ChenYLL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/DimitrovLY14,
author = {Martin Dimitrov and
Yung{-}Hsiang Lu and
Chia{-}Lin Yang},
title = {Guest Editors' Introduction: Cloud Computing for Embedded Systems},
journal = {{IEEE} Des. Test},
volume = {31},
number = {3},
pages = {6--7},
year = {2014},
url = {https://doi.org/10.1109/MDAT.2014.2329242},
doi = {10.1109/MDAT.2014.2329242},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/DimitrovLY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/LiuSYYW14,
author = {Ren{-}Shuo Liu and
De{-}Yu Shen and
Chia{-}Lin Yang and
Shun{-}Chih Yu and
Cheng{-}Yuan Michael Wang},
editor = {Rajeev Balasubramonian and
Al Davis and
Sarita V. Adve},
title = {{NVM} duet: unified working memory and persistent store architecture},
booktitle = {Architectural Support for Programming Languages and Operating Systems,
{ASPLOS} 2014, Salt Lake City, UT, USA, March 1-5, 2014},
pages = {455--470},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2541940.2541957},
doi = {10.1145/2541940.2541957},
timestamp = {Wed, 07 Jul 2021 13:23:08 +0200},
biburl = {https://dblp.org/rec/conf/asplos/LiuSYYW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuCYLHL14,
author = {Ren{-}Shuo Liu and
Meng{-}Yen Chuang and
Chia{-}Lin Yang and
Cheng{-}Hsuan Li and
Kin{-}Chu Ho and
Hsiang{-}Pang Li},
title = {EC-Cache: Exploiting Error Locality to Optimize {LDPC} in {NAND} Flash-Based
SSDs},
booktitle = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
Francisco, CA, USA, June 1-5, 2014},
pages = {145:1--145:6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2593069.2593130},
doi = {10.1145/2593069.2593130},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiuCYLHL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/WangLYCHYLG14,
author = {Po{-}Han Wang and
Gen{-}Hong Liu and
Jen{-}Chieh Yeh and
Tse{-}Min Chen and
Hsu{-}Yao Huang and
Chia{-}Lin Yang and
Shih{-}Lien Liu and
James Greensky},
title = {Full system simulation framework for integrated {CPU/GPU} architecture},
booktitle = {Technical Papers of 2014 International Symposium on {VLSI} Design,
Automation and Test, {VLSI-DAT} 2014, Hsinchu, Taiwan, April 28-30,
2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-DAT.2014.6834872},
doi = {10.1109/VLSI-DAT.2014.6834872},
timestamp = {Tue, 04 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/WangLYCHYLG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuYLC13,
author = {Ren{-}Shuo Liu and
Chia{-}Lin Yang and
Cheng{-}Hsuan Li and
Geng{-}You Chen},
title = {DuraCache: a durable {SSD} cache using {MLC} {NAND} flash},
booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin,
TX, USA, May 29 - June 07, 2013},
pages = {166:1--166:6},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2463209.2488939},
doi = {10.1145/2463209.2488939},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiuYLC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/LinCYL13,
author = {Ping{-}Sheng Lin and
Yi{-}Jung Chen and
Chia{-}Lin Yang and
Yi{-}Chang Lu},
editor = {Pai H. Chou and
Ru Huang and
Yuan Xie and
Tanay Karnik},
title = {Exploring synergistic {DVFS} control of cores and DRAMs for thermal
efficiency in CMPs with 3D-stacked DRAMs},
booktitle = {International Symposium on Low Power Electronics and Design (ISLPED),
Beijing, China, September 4-6, 2013},
pages = {304},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISLPED.2013.6629313},
doi = {10.1109/ISLPED.2013.6629313},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/LinCYL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/MizunumaLY13,
author = {Hitoshi Mizunuma and
Yi{-}Chang Lu and
Chia{-}Lin Yang},
title = {Thermal coupling aware task migration using neighboring core search
for many-core systems},
booktitle = {2013 International Symposium on {VLSI} Design, Automation, and Test,
{VLSI-DAT} 2013, Hsinchu, Taiwan, April 22-24, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLDI-DAT.2013.6533805},
doi = {10.1109/VLDI-DAT.2013.6533805},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/MizunumaLY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LinYHC12,
author = {Ye{-}Jyun Lin and
Chia{-}Lin Yang and
Jiao{-}Wei Huang and
Naehyuck Chang},
title = {Memory access aware power gating for MPSoCs},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {121--126},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6164931},
doi = {10.1109/ASPDAC.2012.6164931},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LinYHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChenHKYW12,
author = {Chi{-}Hao Chen and
Pi{-}Cheng Hsiu and
Tei{-}Wei Kuo and
Chia{-}Lin Yang and
Cheng{-}Yuan Michael Wang},
editor = {Patrick Groeneveld and
Donatella Sciuto and
Soha Hassoun},
title = {Age-based {PCM} wear leveling with nearly zero search cost},
booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
Francisco, CA, USA, June 3-7, 2012},
pages = {453--458},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2228360.2228439},
doi = {10.1145/2228360.2228439},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChenHKYW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fast/LiuYW12,
author = {Ren{-}Shuo Liu and
Chia{-}Lin Yang and
Wei Wu},
editor = {William J. Bolosky and
Jason Flinn},
title = {Optimizing {NAND} flash-based SSDs via retention relaxation},
booktitle = {Proceedings of the 10th {USENIX} conference on File and Storage Technologies,
{FAST} 2012, San Jose, CA, USA, February 14-17, 2012},
pages = {11},
publisher = {{USENIX} Association},
year = {2012},
url = {https://www.usenix.org/conference/fast12/optimizing-nand-flash-based-ssds-retention-relaxation},
timestamp = {Tue, 02 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fast/LiuYW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChenYC12,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Jian{-}Jia Chen},
editor = {Alan J. Hu},
title = {Distributed memory interface synthesis for Network-on-Chips with 3D-stacked
DRAMs},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {458--465},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429479},
doi = {10.1145/2429384.2429479},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ChenYC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LinSCYW12,
author = {Chung{-}Hsiang Lin and
De{-}Yu Shen and
Yi{-}Jung Chen and
Chia{-}Lin Yang and
Cheng{-}Yuan Michael Wang},
title = {{SECRET:} Selective error correction for refresh energy reduction
in DRAMs},
booktitle = {30th International {IEEE} Conference on Computer Design, {ICCD} 2012,
Montreal, QC, Canada, September 30 - Oct. 3, 2012},
pages = {67--74},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ICCD.2012.6378619},
doi = {10.1109/ICCD.2012.6378619},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/LinSCYW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/WangLYC12,
author = {Po{-}Han Wang and
Chien{-}Wei Lo and
Chia{-}Lin Yang and
Yu{-}Jung Cheng},
editor = {Rajeev Balasubramonian and
Vijayalakshmi Srinivasan},
title = {A cycle-level {SIMT-GPU} simulation framework},
booktitle = {2012 {IEEE} International Symposium on Performance Analysis of Systems
{\&} Software, New Brunswick, NJ, USA, April 1-3, 2012},
pages = {114--115},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISPASS.2012.6189213},
doi = {10.1109/ISPASS.2012.6189213},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispass/WangLYC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijebm/ChenCLCY11,
author = {James C. Chen and
Kou{-}Huang Chen and
Chien{-}Hsin Lin and
Chia{-}Wen Chen and
Chia{-}Lin Yang},
title = {A Study of a Heuristic Capacity Planning Algorithm for Weapon Production
System},
journal = {Int. J. Electron. Bus. Manag.},
volume = {9},
number = {1},
pages = {46--57},
year = {2011},
url = {http://ijebm.ie.nthu.edu.tw/IJEBM\_Web/IJEBM\_static/Paper-V9\_N1/A05.pdf},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijebm/ChenCLCY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/WangYCC11,
author = {Po{-}Han Wang and
Chia{-}Lin Yang and
Yen{-}Ming Chen and
Yu{-}Jung Cheng},
title = {Power gating strategies on GPUs},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {3},
pages = {13:1--13:25},
year = {2011},
url = {https://doi.org/10.1145/2019608.2019612},
doi = {10.1145/2019608.2019612},
timestamp = {Tue, 04 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/WangYCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ChenYCC11,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Jaw{-}Wei Chi and
Jian{-}Jia Chen},
title = {{TACLC:} Timing-Aware Cache Leakage Control for Hard Real-Time Systems},
journal = {{IEEE} Trans. Computers},
volume = {60},
number = {6},
pages = {767--782},
year = {2011},
url = {https://doi.org/10.1109/TC.2011.44},
doi = {10.1109/TC.2011.44},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/ChenYCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MizunumaLY11,
author = {Hitoshi Mizunuma and
Yi{-}Chang Lu and
Chia{-}Lin Yang},
title = {Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel
Cooling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1293--1306},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2144596},
doi = {10.1109/TCAD.2011.2144596},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MizunumaLY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/YuhLHHYC11,
author = {Ping{-}Hung Yuh and
Cliff Chiung{-}Yu Lin and
Tsung{-}Wei Huang and
Tsung{-}Yi Ho and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
editor = {Janet Meiling Wang and
Deming Chen},
title = {A SAT-based routing algorithm for cross-referencing biochips},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135436},
doi = {10.1109/SLIP.2011.6135436},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/YuhLHHYC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChenYW10,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Po{-}Han Wang},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {{PM-COSYN:} {PE} and memory co-synthesis for MPSoCs},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1590--1595},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457064},
doi = {10.1109/DATE.2010.5457064},
timestamp = {Tue, 04 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/ChenYW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LinYLHC10,
author = {Ye{-}Jyun Lin and
Chia{-}Lin Yang and
Tay{-}Jyi Lin and
Jiao{-}Wei Huang and
Naehyuck Chang},
editor = {Louis Scheffer and
Joel R. Phillips and
Alan J. Hu},
title = {Hierarchical memory scheduling for multimedia MPSoCs},
booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
San Jose, CA, USA, November 7-11, 2010},
pages = {190--196},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICCAD.2010.5654145},
doi = {10.1109/ICCAD.2010.5654145},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LinYLHC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iiswc/LiuTY10,
author = {Ren{-}Shuo Liu and
Yun{-}Cheng Tsai and
Chia{-}Lin Yang},
title = {Parallelization and characterization of {GARCH} option pricing on
GPUs},
booktitle = {Proceedings of the 2010 {IEEE} International Symposium on Workload
Characterization, {IISWC} 2010, Atlanta, GA, USA, December 2-4, 2010},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/IISWC.2010.5648864},
doi = {10.1109/IISWC.2010.5648864},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iiswc/LiuTY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ParkCSKYC10,
author = {Sangyoung Park and
Jian{-}Jia Chen and
Donghwa Shin and
Younghyun Kim and
Chia{-}Lin Yang and
Naehyuck Chang},
editor = {Vojin G. Oklobdzija and
Barry Pangle and
Naehyuck Chang and
Naresh R. Shanbhag and
Chris H. Kim},
title = {Dynamic thermal management for networked embedded systems under harsh
ambient temperature variation},
booktitle = {Proceedings of the 2010 International Symposium on Low Power Electronics
and Design, 2010, Austin, Texas, USA, August 18-20, 2010},
pages = {289--294},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1840845.1840905},
doi = {10.1145/1840845.1840905},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/ParkCSKYC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/ChengLLY10,
author = {Hsiang{-}Yun Cheng and
Chung{-}Hsiang Lin and
Jian Li and
Chia{-}Lin Yang},
title = {Memory Latency Reduction via Thread Throttling},
booktitle = {43rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
{MICRO} 2010, 4-8 December 2010, Atlanta, Georgia, {USA}},
pages = {53--64},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/MICRO.2010.39},
doi = {10.1109/MICRO.2010.39},
timestamp = {Tue, 31 May 2022 14:39:58 +0200},
biburl = {https://dblp.org/rec/conf/micro/ChengLLY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/WangCYC09,
author = {Po{-}Han Wang and
Yen{-}Ming Chen and
Chia{-}Lin Yang and
Yu{-}Jung Cheng},
title = {A Predictive Shutdown Technique for {GPU} Shader Processors},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {8},
number = {1},
pages = {9--12},
year = {2009},
url = {https://doi.org/10.1109/L-CA.2009.1},
doi = {10.1109/L-CA.2009.1},
timestamp = {Tue, 04 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cal/WangCYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/ChenYC09,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Yen{-}Sheng Chang},
title = {An architectural co-synthesis algorithm for energy-aware Network-on-Chip
design},
journal = {J. Syst. Archit.},
volume = {55},
number = {5-6},
pages = {299--309},
year = {2009},
url = {https://doi.org/10.1016/j.sysarc.2009.02.002},
doi = {10.1016/J.SYSARC.2009.02.002},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/ChenYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuhSYC09,
author = {Ping{-}Hung Yuh and
Sachin S. Sapatnekar and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
title = {A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing
Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1295--1306},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2023196},
doi = {10.1109/TCAD.2009.2023196},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuhSYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/YuhYC09,
author = {Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
title = {T-trees: {A} tree-based representation for temporal and three-dimensional
floorplanning},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {14},
number = {4},
pages = {51:1--51:28},
year = {2009},
url = {https://doi.org/10.1145/1562514.1562519},
doi = {10.1145/1562514.1562519},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/YuhYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/YuhYLL09,
author = {Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Chi{-}Feng Li and
Chung{-}Hsiang Lin},
title = {Leakage-aware task scheduling for partially dynamically reconfigurable
FPGAs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {14},
number = {4},
pages = {52:1--52:26},
year = {2009},
url = {https://doi.org/10.1145/1562514.1562520},
doi = {10.1145/1562514.1562520},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/YuhYLL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/WangYCYW09,
author = {Sung{-}Wen Wang and
Shu{-}Sian Yang and
Hong{-}Ming Chen and
Chia{-}Lin Yang and
Ja{-}Ling Wu},
title = {A Multi-core Architecture Based Parallel Framework for {H.264/AVC}
Deblocking Filters},
journal = {J. Signal Process. Syst.},
volume = {57},
number = {2},
pages = {195--211},
year = {2009},
url = {https://doi.org/10.1007/s11265-008-0321-4},
doi = {10.1007/S11265-008-0321-4},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/WangYCYW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MizunumaYL09,
author = {Hitoshi Mizunuma and
Chia{-}Lin Yang and
Yi{-}Chang Lu},
editor = {Jaijeet S. Roychowdhury},
title = {Thermal modeling for 3D-ICs with integrated microchannel cooling},
booktitle = {2009 International Conference on Computer-Aided Design, {ICCAD} 2009,
San Jose, CA, USA, November 2-5, 2009},
pages = {256--263},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1687399.1687447},
doi = {10.1145/1687399.1687447},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/MizunumaYL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/LinYK09,
author = {Chung{-}Hsiang Lin and
Chia{-}Lin Yang and
Ku{-}Jei King},
editor = {J{\"{o}}rg Henkel and
Ali Keshavarzi and
Naehyuck Chang and
Tahir Ghani},
title = {{PPT:} joint performance/power/thermal management of {DRAM} memory
for multi-core systems},
booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics
and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
pages = {93--98},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1594233.1594255},
doi = {10.1145/1594233.1594255},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/LinYK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinCLCY08,
author = {Chung{-}Wei Lin and
Szu{-}Yu Chen and
Chi{-}Feng Li and
Yao{-}Wen Chang and
Chia{-}Lin Yang},
title = {Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning
Graphs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {643--653},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917583},
doi = {10.1109/TCAD.2008.917583},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinCLCY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuhYC08,
author = {Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
title = {BioRoute: {A} Network-Flow-Based Routing Algorithm for the Synthesis
of Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {1928--1941},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006140},
doi = {10.1109/TCAD.2008.2006140},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuhYC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiYT08,
author = {Han{-}Lin Li and
Chia{-}Lin Yang and
Hung{-}Wei Tseng},
title = {Energy-Aware Flash Memory Management in Virtual Memory System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {8},
pages = {952--964},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2000517},
doi = {10.1109/TVLSI.2008.2000517},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiYT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/YuhSYC08,
author = {Ping{-}Hung Yuh and
Sachin S. Sapatnekar and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
editor = {Limor Fix},
title = {A progressive-ILP based routing algorithm for cross-referencing biochips},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {284--289},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391541},
doi = {10.1145/1391469.1391541},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/YuhSYC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/YuhYC07,
author = {Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
title = {Placement of defect-tolerant digital microfluidic biochips using the
T-tree formulation},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {3},
number = {3},
pages = {13},
year = {2007},
url = {https://doi.org/10.1145/1295231.1295234},
doi = {10.1145/1295231.1295234},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/YuhYC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/YuhYC07,
author = {Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
title = {Temporal floorplanning using the three-dimensional transitive closure
subGraph},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {12},
number = {4},
pages = {37},
year = {2007},
url = {https://doi.org/10.1145/1278349.1278350},
doi = {10.1145/1278349.1278350},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/YuhYC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/ChiYCC07,
author = {Jaw{-}Wei Chi and
Chia{-}Lin Yang and
Yi{-}Jung Chen and
Jian{-}Jia Chen},
editor = {Taewhan Kim and
Pascal Sainrat and
Steven S. Lumetta and
Nacho Navarro},
title = {Cache leakage control mechanism for hard real-time systems},
booktitle = {Proceedings of the 2007 International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, {CASES} 2007, Salzburg, Austria,
September 30 - October 3, 2007},
pages = {248--256},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1289881.1289924},
doi = {10.1145/1289881.1289924},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/ChiYCC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChenKYK07,
author = {Jian{-}Jia Chen and
Tei{-}Wei Kuo and
Chia{-}Lin Yang and
Ku{-}Jei King},
editor = {Rudy Lauwereins and
Jan Madsen},
title = {Energy-efficient real-time task scheduling with task rejection},
booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition,
{DATE} 2007, Nice, France, April 16-20, 2007},
pages = {1629--1634},
publisher = {{EDA} Consortium, San Jose, CA, {USA}},
year = {2007},
url = {https://dl.acm.org/citation.cfm?id=1266724},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/ChenKYK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YuhYC07,
author = {Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
editor = {Georges G. E. Gielen},
title = {BioRoute: a network-flow based routing algorithm for digital microfluidic
biochips},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {752--757},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397356},
doi = {10.1109/ICCAD.2007.4397356},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/YuhYC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icmcs/ChienSKYCKC07,
author = {Shao{-}Yi Chien and
Chi{-}Sheng Shih and
Mong{-}Kai Ku and
Chia{-}Lin Yang and
Yao{-}Wen Chang and
Tei{-}Wei Kuo and
Liang{-}Gee Chen},
title = {3D Video Applications and Intelligent Video Surveillance Camera and
its {VLSI} Design},
booktitle = {Proceedings of the 2007 {IEEE} International Conference on Multimedia
and Expo, {ICME} 2007, July 2-5, 2007, Beijing, China},
pages = {9},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICME.2007.4284571},
doi = {10.1109/ICME.2007.4284571},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icmcs/ChienSKYCKC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/LiYYC07,
author = {Chi{-}Feng Li and
Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
editor = {Diana Marculescu and
Anand Raghunathan and
Ali Keshavarzi and
Vijaykrishnan Narayanan},
title = {Post-placement leakage optimization for partially dynamically reconfigurable
FPGAs},
booktitle = {Proceedings of the 2007 International Symposium on Low Power Electronics
and Design, 2007, Portland, OR, USA, August 27-29, 2007},
pages = {92--97},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1283780.1283801},
doi = {10.1145/1283780.1283801},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/LiYYC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/LinCLCY07,
author = {Chung{-}Wei Lin and
Szu{-}Yu Chen and
Chi{-}Feng Li and
Yao{-}Wen Chang and
Chia{-}Lin Yang},
editor = {Patrick H. Madden and
David Z. Pan},
title = {Efficient obstacle-avoiding rectilinear steiner tree construction},
booktitle = {Proceedings of the 2007 International Symposium on Physical Design,
{ISPD} 2007, Austin, Texas, USA, March 18-21, 2007},
pages = {127--134},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231996.1232023},
doi = {10.1145/1231996.1232023},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/LinCLCY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sac/HungCYCS07,
author = {Wei{-}Hsuan Hung and
Yi{-}Jung Chen and
Chia{-}Lin Yang and
Yen{-}Sheng Chang and
Alan P. Su},
editor = {Yookun Cho and
Roger L. Wainwright and
Hisham Haddad and
Sung Y. Shin and
Yong Wan Koo},
title = {An architectural co-synthesis algorithm for energy-aware network-on-chip
design},
booktitle = {Proceedings of the 2007 {ACM} Symposium on Applied Computing (SAC),
Seoul, Korea, March 11-15, 2007},
pages = {680--684},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1244002.1244156},
doi = {10.1145/1244002.1244156},
timestamp = {Sun, 02 Jun 2019 21:18:37 +0200},
biburl = {https://dblp.org/rec/conf/sac/HungCYCS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aPcsac/YangWC06,
author = {Chia{-}Lin Yang and
Shun{-}Ying Wang and
Yi{-}Jung Chen},
editor = {Chris R. Jesshope and
Colin Egan},
title = {Branch Behavior Characterization for Multimedia Applications},
booktitle = {Advances in Computer Systems Architecture, 11th Asia-Pacific Conference,
{ACSAC} 2006, Shanghai, China, September 6-8, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4186},
pages = {523--530},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11859802\_53},
doi = {10.1007/11859802\_53},
timestamp = {Tue, 14 May 2019 10:00:42 +0200},
biburl = {https://dblp.org/rec/conf/aPcsac/YangWC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/YuhYC06,
author = {Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
editor = {Ellen Sentovich},
title = {Placement of digital microfluidic biochips using the t-tree formulation},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {931--934},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1147145},
doi = {10.1145/1146909.1147145},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/YuhYC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/LinYK06,
author = {Chung{-}Hsiang Lin and
Chia{-}Lin Yang and
Ku{-}Jei King},
editor = {Wolfgang Nebel and
Mircea R. Stan and
Anand Raghunathan and
J{\"{o}}rg Henkel and
Diana Marculescu},
title = {Hierarchical value cache encoding for off-chip data bus},
booktitle = {Proceedings of the 2006 International Symposium on Low Power Electronics
and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006},
pages = {143--146},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1165573.1165607},
doi = {10.1145/1165573.1165607},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/LinYK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/TsengLY06,
author = {Hung{-}Wei Tseng and
Han{-}Lin Li and
Chia{-}Lin Yang},
editor = {Wolfgang Nebel and
Mircea R. Stan and
Anand Raghunathan and
J{\"{o}}rg Henkel and
Diana Marculescu},
title = {An energy-efficient virtual memory system with flash memory as the
secondary storage},
booktitle = {Proceedings of the 2006 International Symposium on Low Power Electronics
and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006},
pages = {418--423},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1165573.1165675},
doi = {10.1145/1165573.1165675},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/TsengLY06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isorc/WuKY06,
author = {Chin{-}Hsien Wu and
Tei{-}Wei Kuo and
Chia{-}Lin Yang},
title = {A Space-Efficient Caching Mechanism for Flash-Memory Address Translation},
booktitle = {Ninth {IEEE} International Symposium on Object-Oriented Real-Time
Distributed Computing {(ISORC} 2006), 24-26 April 2006, Gyeongju,
Korea},
pages = {64--71},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISORC.2006.13},
doi = {10.1109/ISORC.2006.13},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isorc/WuKY06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcsv/YangTHW05,
author = {Chia{-}Lin Yang and
Hong{-}Wei Tseng and
Chia{-}Chiang Ho and
Ja{-}Ling Wu},
title = {Software-Controlled Cache Architecture for Energy Efficiency},
journal = {{IEEE} Trans. Circuits Syst. Video Technol.},
volume = {15},
number = {5},
pages = {634--644},
year = {2005},
url = {https://doi.org/10.1109/TCSVT.2005.846444},
doi = {10.1109/TCSVT.2005.846444},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcsv/YangTHW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aPcsac/ChenYH05,
author = {Chun{-}Yang Chen and
Chia{-}Lin Yang and
Shih{-}Hao Hung},
editor = {Thambipillai Srikanthan and
Jingling Xue and
Chip{-}Hong Chang},
title = {Cache Leakage Management for Multi-programming Workloads},
booktitle = {Advances in Computer Systems Architecture, 10th Asia-Pacific Conference,
{ACSAC} 2005, Singapore, October 24-26, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3740},
pages = {736--749},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11572961\_60},
doi = {10.1007/11572961\_60},
timestamp = {Tue, 14 May 2019 10:00:42 +0200},
biburl = {https://dblp.org/rec/conf/aPcsac/ChenYH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/WuYYC05,
author = {Yen{-}Wei Wu and
Chia{-}Lin Yang and
Ping{-}Hung Yuh and
Yao{-}Wen Chang},
editor = {Kaushik Roy and
Vivek Tiwari},
title = {Joint exploration of architectural and physical design spaces with
thermal consideration},
booktitle = {Proceedings of the 2005 International Symposium on Low Power Electronics
and Design, 2005, San Diego, California, USA, August 8-10, 2005},
pages = {123--126},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1077603.1077636},
doi = {10.1145/1077603.1077636},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/WuYYC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/ShihYKKCCC05,
author = {Chi{-}Sheng Shih and
Chia{-}Lin Yang and
Mong{-}Kai Ku and
Tei{-}Wei Kuo and
Shao{-}Yi Chien and
Yao{-}Wen Chang and
Liang{-}Gee Chen},
title = {Reconfigurable Platform for Content Science Research},
booktitle = {11th {IEEE} International Conference on Embedded and Real-Time Computing
Systems and Applications {(RTCSA} 2005), 17-19 August 2005, Hong Kong,
China},
pages = {481--486},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/RTCSA.2005.79},
doi = {10.1109/RTCSA.2005.79},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtcsa/ShihYKKCCC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/YangLTL04,
author = {Chia{-}Lin Yang and
Alvin R. Lebeck and
Hung{-}Wei Tseng and
Chien{-}Hao Lee},
title = {Tolerating memory latency through push prefetching for pointer-intensive
applications},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {1},
number = {4},
pages = {445--475},
year = {2004},
url = {https://doi.org/10.1145/1044823.1044827},
doi = {10.1145/1044823.1044827},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/YangLTL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangLY04,
author = {Yen{-}Jen Chang and
Feipei Lai and
Chia{-}Lin Yang},
title = {Zero-aware asymmetric {SRAM} cell for reducing cache power in writing
zero},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {12},
number = {8},
pages = {827--836},
year = {2004},
url = {https://doi.org/10.1109/TVLSI.2004.831471},
doi = {10.1109/TVLSI.2004.831471},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangLY04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YuhYCC04,
author = {Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Yao{-}Wen Chang and
Hsin{-}Lung Chen},
editor = {Masaharu Imai},
title = {Temporal floorplanning using 3D-subTCG},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {725--730},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.190},
doi = {10.1109/ASPDAC.2004.190},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/YuhYCC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/WuKY04,
author = {Chin{-}Hsien Wu and
Tei{-}Wei Kuo and
Chia{-}Lin Yang},
editor = {Alex Orailoglu and
Pai H. Chou and
Petru Eles and
Axel Jantsch},
title = {Energy-efficient flash-memory storage systems with an interrupt-emulation
mechanism},
booktitle = {Proceedings of the 2nd {IEEE/ACM/IFIP} International Conference on
Hardware/Software Codesign and System Synthesis, {CODES+ISSS} 2004,
Stockholm, Sweden, September 8-10, 2004},
pages = {134--139},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/1016720.1016755},
doi = {10.1145/1016720.1016755},
timestamp = {Wed, 04 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/codes/WuKY04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChangYL04,
author = {Yen{-}Jen Chang and
Chia{-}Lin Yang and
Feipei Lai},
title = {Value-Conscious Cache: Simple Technique for Reducing Cache Access
Power},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {16--21},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1268821},
doi = {10.1109/DATE.2004.1268821},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ChangYL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ecrts/ChenHCYPK04,
author = {Jian{-}Jia Chen and
Heng{-}Ruey Hsu and
Kai{-}Hsiang Chuang and
Chia{-}Lin Yang and
Ai{-}Chun Pang and
Tei{-}Wei Kuo},
title = {Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations},
booktitle = {16th Euromicro Conference on Real-Time Systems {(ECRTS} 2004), 30
June - 2 July 1004, Catania, Italy, Proceedings},
pages = {101--108},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ECRTS.2004.20},
doi = {10.1109/ECRTS.2004.20},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ecrts/ChenHCYPK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YuhYC04,
author = {Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
title = {Temporal floorplanning using the T-tree formulation},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {300--305},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382590},
doi = {10.1109/ICCAD.2004.1382590},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/YuhYC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/YangL04,
author = {Chia{-}Lin Yang and
Chien{-}Hao Lee},
editor = {Rajiv V. Joshi and
Kiyoung Choi and
Vivek Tiwari and
Kaushik Roy},
title = {HotSpot cache: joint temporal and spatial locality exploitation for
i-cache energy reduction},
booktitle = {Proceedings of the 2004 International Symposium on Low Power Electronics
and Design, 2004, Newport Beach, California, USA, August 9-11, 2004},
pages = {114--119},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/1013235.1013270},
doi = {10.1145/1013235.1013270},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/YangL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pcm/ShihYT04,
author = {Tse{-}Tsung Shih and
Chia{-}Lin Yang and
Yi{-}Shin Tung},
editor = {Kiyoharu Aizawa and
Yuichi Nakamura and
Shin'ichi Satoh},
title = {Workload Characterization of the {H.264/AVC} Decoder},
booktitle = {Advances in Multimedia Information Processing - {PCM} 2004, 5th Pacific
Rim Conference on Multimedia, Tokyo, Japan, November 30 - December
3, 2004, Proceedings, Part {II}},
series = {Lecture Notes in Computer Science},
volume = {3332},
pages = {957--966},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30542-2\_118},
doi = {10.1007/978-3-540-30542-2\_118},
timestamp = {Fri, 10 Mar 2023 14:55:31 +0100},
biburl = {https://dblp.org/rec/conf/pcm/ShihYT04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sac/ChenKY04,
author = {Jian{-}Jia Chen and
Tei{-}Wei Kuo and
Chia{-}Lin Yang},
editor = {Hisham Haddad and
Andrea Omicini and
Roger L. Wainwright and
Lorie M. Liebrock},
title = {Profit-driven uniprocessor scheduling with energy and timing constraints},
booktitle = {Proceedings of the 2004 {ACM} Symposium on Applied Computing (SAC),
Nicosia, Cyprus, March 14-17, 2004},
pages = {834--840},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/967900.968072},
doi = {10.1145/967900.968072},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sac/ChenKY04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChangYL03,
author = {Yen{-}Jen Chang and
Chia{-}Lin Yang and
Feipei Lai},
editor = {Ingrid Verbauwhede and
Hyung Roh},
title = {A power-aware {SWDR} cell for reducing cache write power},
booktitle = {Proceedings of the 2003 International Symposium on Low Power Electronics
and Design, 2003, Seoul, Korea, August 25-27, 2003},
pages = {14--17},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/871506.871513},
doi = {10.1145/871506.871513},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ChangYL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ishpc/YangL02,
author = {Chia{-}Lin Yang and
Alvin R. Lebeck},
editor = {Hans P. Zima and
Kazuki Joe and
Mitsuhisa Sato and
Yoshiki Seo and
Masaaki Shimasaki},
title = {A Programmable Memory Hierarchy for Prefetching Linked Data Structures},
booktitle = {High Performance Computing, 4th International Symposium, {ISHPC} 2002,
Kansai Science City, Japan, May 15-17, 2002, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2327},
pages = {160--174},
publisher = {Springer},
year = {2002},
url = {https://doi.org/10.1007/3-540-47847-7\_15},
doi = {10.1007/3-540-47847-7\_15},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/ishpc/YangL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pcm/MaY02,
author = {Wan{-}Chun Ma and
Chia{-}Lin Yang},
editor = {Yung{-}Chang Chen and
Long{-}Wen Chang and
Chiou{-}Ting Hsu},
title = {Using Intel Streaming {SIMD} Extensions for 3D Geometry Processing},
booktitle = {Advances in Multimedia Information Processing - {PCM} 2002, Third
{IEEE} Pacific Rim Conference on Multimedia, Hsinchu, Taiwan, December
16-18, 2002, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2532},
pages = {1080--1087},
publisher = {Springer},
year = {2002},
url = {https://doi.org/10.1007/3-540-36228-2\_134},
doi = {10.1007/3-540-36228-2\_134},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/pcm/MaY02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/YangSL00,
author = {Chia{-}Lin Yang and
Barton Sano and
Alvin R. Lebeck},
title = {Exploiting Parallelism in Geometry Processing with General Purpose
Processors and Floating-Point {SIMD} Instructions},
journal = {{IEEE} Trans. Computers},
volume = {49},
number = {9},
pages = {934--946},
year = {2000},
url = {https://doi.org/10.1109/12.869324},
doi = {10.1109/12.869324},
timestamp = {Thu, 08 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/YangSL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/YangL00,
author = {Chia{-}Lin Yang and
Alvin R. Lebeck},
editor = {John Reynders and
Alexander V. Veidenbaum},
title = {Push vs. pull: data movement for linked data structures},
booktitle = {Proceedings of the 14th international conference on Supercomputing,
{ICS} 2000, Santa Fe, NM, USA, May 8-11, 2000},
pages = {176--186},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/335231.335248},
doi = {10.1145/335231.335248},
timestamp = {Tue, 06 Nov 2018 11:07:02 +0100},
biburl = {https://dblp.org/rec/conf/ics/YangL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/europar/LebeckRYT99,
author = {Alvin R. Lebeck and
David R. Raymond and
Chia{-}Lin Yang and
Mithuna Thottethodi},
editor = {Patrick Amestoy and
Philippe Berger and
Michel J. Dayd{\'{e}} and
Iain S. Duff and
Val{\'{e}}rie Frayss{\'{e}} and
Luc Giraud and
Daniel Ruiz},
title = {Annotated Memory References: {A} Mechanism for Informed Cache Management},
booktitle = {Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference,
Toulouse, France, August 31 - September 3, 1999, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1685},
pages = {1251--1254},
publisher = {Springer},
year = {1999},
url = {https://doi.org/10.1007/3-540-48311-X\_177},
doi = {10.1007/3-540-48311-X\_177},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/europar/LebeckRYT99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/YangSL98,
author = {Chia{-}Lin Yang and
Barton Sano and
Alvin R. Lebeck},
editor = {James O. Bondi and
Jim Smith},
title = {Exploiting Instruction Level Parallelism in Geometry Processing for
Three Dimensional Graphics Applications},
booktitle = {Proceedings of the 31st Annual {IEEE/ACM} International Symposium
on Microarchitecture, {MICRO} 31, Dallas, Texas, USA, November 30
- December 2, 1998},
pages = {14--24},
publisher = {{ACM/IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/MICRO.1998.742765},
doi = {10.1109/MICRO.1998.742765},
timestamp = {Tue, 31 May 2022 14:39:58 +0200},
biburl = {https://dblp.org/rec/conf/micro/YangSL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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