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ORCIDJosé Luís Güntzel
José Luís Almada Güntzel
Person information
- affiliation: Federal University of Santa Catarina, Embedded Computing Laboratory, Florianópolis, Brazil
- affiliation (PhD 2000): Federal University of Rio Grande do Sul, Brazil
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2020 – today
- 2024
[j9]Tiago Augusto Fontana
, Erfan Aghaeekiasaraee, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, Laleh Behjat, José Luís Güntzel:
ILPGRC: ILP-Based Global Routing Optimization With Cell Movements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 352-365 (2024)- 2023
- [j8]Erfan Aghaeekiasaraee, Aysa Fakheri Tabrizi, Tiago Augusto Fontana, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, José Luís Güntzel, David T. Westwick, Laleh Behjat:
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes. ACM Trans. Design Autom. Electr. Syst. 28(5): 79:1-79:42 (2023) - [c66]André Beims Bräscher, Gabriela Furtado Da Silveira, Luiz Henrique Cancellier, Ismael Seidel, Mateus Grellert, José Luís Güntzel:
A New Approach to Video Coding Leveraging Hybrid Coding and Video Frame Interpolation. SBCCI 2023: 1-6 - [c65]Vanio Rodrigues Filho, Ismael Seidel, Nicole Citadin, Marcio Monteiro, Mateus Grellert, José Luís Güntzel:
Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FME. SBCCI 2023: 1-6 - 2022
- [j7]Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla, Laleh Behjat, José Luís Güntzel:
Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1481-1494 (2022) - [c64]Luiz Henrique Cancellier, Mateus Grellert, José Luís Güntzel, Luís Alberto da Silva Cruz:
Autoencoder Model Exploration for Multi-Layer Video Compression. EUVIP 2022: 1-6 - [c63]Sheiny Fabre Almeida, Aysa Fakheri Tabrizi, Erfan Aghaeekiasaraee, Renan Netto, Tiago Augusto Fontana, Upma Gandhi, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt:
E-RVP: An Initial Design Rule Violation Predictor Using Placement Information. ICECS 2022 2022: 1-4 - [c62]Marcio Monteiro, Ismael Seidel, Mateus Grellert, José Luís Güntzel, Leonardo Bandeira Soares, Cristina Meinhardt:
Exploring the Impacts of Multiple Kernel Sizes of Gaussian Filters Combined to Approximate Computing in Canny Edge Detection. LASCAS 2022: 1-4 - [c61]Sheiny Fabre Almeida, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt:
Routability-Driven Detailed Placement Using Reinforcement Learning. VLSI-SoC 2022: 1-2 - 2021
- [c60]Gabriel B. Sant'Anna, Luiz Henrique Cancellier, Ismael Seidel, Mateus Grellert, José Luís Güntzel:
Relying on a Rate Constraint to Reduce Motion Estimation Complexity. ICASSP 2021: 1560-1564 - [c59]Marcio Monteiro, Pedro Aquino Silva, Ismael Seidel, Mateus Grellert, Leonardo Bandeira Soares, José Luís Güntzel, Cristina Meinhardt:
Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders. ISCAS 2021: 1-5 - [c58]Tiago Augusto Fontana, Erfan Aghaeekiasaraee, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat, José Luís Güntzel:
ILP-Based Global Routing Optimization with Cell Movements. ISVLSI 2021: 25-30 - [c57]Vanio Rodrigues Filho, Marcio Monteiro, Ismael Seidel, Mateus Grellert, José Luís Güntzel:
Hardware-Friendly Search Patterns for the Versatile Video Coding Fractional Motion Estimation. MMSP 2021: 1-6 - [c56]Ismael Seidel, Vanio Rodrigues Filho, Mateus Grellert, Luciano Volcan Agostini, José Luís Güntzel:
SAD or SATD? How the Distortion Metric Impacts a Fractional Motion Estimation VLSI Architecture. MMSP 2021: 1-6 - 2020
- [j6]Michael Hübner, José Luís Güntzel:
Guest Editors' Introduction: SBCCI 2018. IEEE Des. Test 37(3): 5-6 (2020) - [c55]Vanio Rodrigues Filho, Marcio Monteiro, Ismael Seidel, Mateus Grellert, José Luís Güntzel:
Standalone Rate-Distortion FME Architecture. SBCCI 2020: 1-6
2010 – 2019
- 2019
- [j5]Ismael Seidel, Marcio Monteiro, Bruno Bonotto, Luciano Volcan Agostini, José Luís Güntzel:
Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation Reuse. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2102-2115 (2019) - [c54]Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla, José Luís Güntzel:
How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization. ISPD 2019: 3-10 - 2018
- [c53]Luiz Henrique Cancellier, Ismael Seidel, José Luís Güntzel:
On HEVC Robustness to Integer Motion Estimation Pruning. ICECS 2018: 197-200 - [c52]Douglas Lohmann, Alexis Huf, Djones Lettnin, Frank Siqueira, José Luís Güntzel:
A Domain-specific Language for Automated Fault Injection in SystemC Models. ICECS 2018: 425-428 - [c51]Ismael Seidel, Vanio Rodrigues Filho, Luciano Volcan Agostini, José Luís Güntzel:
Coding- and Energy-Efficient FME Hardware Design. ISCAS 2018: 1-5 - [c50]Marcio Monteiro, Ismael Seidel, José Luís Güntzel:
On the calculation reuse in hadamard-based SATD. LASCAS 2018: 1-4 - [c49]Sheiny Fabre, José Luís Güntzel, Laércio Lima Pilla, Renan Netto, Tiago Fontana, Vinicius S. Livramento:
Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning. SBCCI 2018: 1-6 - 2017
- [j4]Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos:
Incremental Layer Assignment Driven by an External Signoff Timing Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1126-1139 (2017) - [c48]Tiago Fontana, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Sheiny Almeida, Laércio Lima Pilla, José Luís Güntzel:
How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library. ISPD 2017: 25-31 - [c47]Luiz Henrique Cancellier, Ismael Seidel, José Luís Güntzel:
Block matching hardware architecture for SATD-based successive elimination. SBCCI 2017: 149-154 - [c46]André Beims Bräscher, Ismael Seidel, José Luís Güntzel:
Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE. SBCCI 2017: 155-161 - [c45]Tiago Augusto Fontana, Sheiny Almeida, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Laércio Lima Pilla, José Luís Güntzel:
Exploiting cache locality to speedup register clustering. SBCCI 2017: 191-197 - 2016
- [j3]Vinicius S. Livramento, Renan Netto, Chrystian Guth, José Luís Güntzel, Luiz Cláudio Villar dos Santos:
Clock-Tree-Aware Incremental Timing-Driven Placement. ACM Trans. Design Autom. Electr. Syst. 21(3): 38:1-38:27 (2016) - [c44]Renan Netto, Chrystian Guth, Vinicius S. Livramento, Márcio Castro, Laércio Lima Pilla, José Luís Güntzel:
Exploiting parallelism to speed up circuit legalization. ICECS 2016: 624-627 - [c43]Ismael Seidel, José Luís Güntzel, Luciano Volcan Agostini:
Coarse grain partial distortion elimination for Hadamard ME in HEVC. ICECS 2016: 704-707 - [c42]Ismael Seidel, Luiz Henrique Cancellier, José Luís Almada Güntzel, Luciano Volcan Agostini:
Rate-constrained successive elimination of Hadamard-based SATDs. ICIP 2016: 2395-2399 - [c41]Ismael Seidel, André Beims Bräscher, José Luís Almada Güntzel, Luciano Volcan Agostini:
Energy-efficient SATD for beyond HEVC. ISCAS 2016: 802-805 - [c40]Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos, José Luís Güntzel:
Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees. ISVLSI 2016: 36-41 - [c39]Ismael Seidel, Marcio Monteiro, José Luís Almada Güntzel, Luciano Volcan Agostini:
Squarer exploration for energy-efficient sum of squared differences. LASCAS 2016: 327-330 - [c38]Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos, José Luís Güntzel:
Evaluating the impact of circuit legalization on incremental optimization techniques. SBCCI 2016: 1-6 - 2015
- [c37]Vinicius S. Livramento, Chrystian Guth, Renan Netto, José Luís Almada Güntzel, Luiz C. V. dos Santos:
Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization. ICCAD 2015: 528-535 - [c36]Chrystian Guth, Vinicius S. Livramento, Renan Netto, Renan Fonseca, José Luís Güntzel, Luiz C. V. dos Santos:
Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression. ISPD 2015: 141-148 - [c35]Jucemar Monteiro, Guilherme Flach, Marcelo O. Johann, José Luís Almada Güntzel:
An analytical timing-driven algorithm for detailed placement. LASCAS 2015: 1-4 - [c34]Ismael Seidel, André Beims Bräscher, José Luís Güntzel:
Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency. PATMOS 2015: 177-184 - 2014
- [j2]Vinicius S. Livramento, Chrystian Guth, José Luís Almada Güntzel, Marcelo O. Johann:
A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation. ACM Trans. Design Autom. Electr. Syst. 19(4): 40:1-40:25 (2014) - [c33]Luiz Henrique Cancellier, André Beims Bräscher, Ismael Seidel, José Luís Güntzel:
Energy-Efficient Hadamard-Based SATD Architectures. SBCCI 2014: 36:1-36:6 - 2013
- [c32]Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann:
Fast and efficient lagrangian relaxation-based discrete gate sizing. DATE 2013: 1855-1860 - [c31]Ismael Seidel, Bruno George de Moraes, Emilio Wuerges, José Luís Almada Güntzel:
Quality assessment of subsampling patterns for pel decimation targeting high definition video. ICME 2013: 1-6 - [c30]Ismael Seidel, Bruno George de Moraes, José Luís Güntzel:
A low-power configurable VLSI architecture for sum of absolute differences calculation. LASCAS 2013: 1-4 - [c29]Edson Sorato, Renan Netto, Pedro Michel, José Luís Güntzel, Adalbery R. Castro, Aldebaro Klautau:
VLSI architectures for Digital Modulation Classification using Support Vector Machines. LASCAS 2013: 1-4 - [c28]Ismael Seidel, Bruno George de Moraes, André Beims Bräscher, José Luís Güntzel:
On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation. SBCCI 2013: 1-6 - [c27]Edson Sorato, Eduardo P. Fronza, Paulo R. F. M. M. Barbosa, José Luís Almada Güntzel, Adalbery R. Castro, Aldebaro Klautau:
Real-time digital modulation classification based on Support Vector Machines. SBCCI 2013: 1-6 - 2012
- [c26]Vinicius dos S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann:
Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization. ICECS 2012: 468-471 - [c25]Rafael Westphal, José Luís Almada Güntzel, Luiz Cláudio Villar dos Santos:
Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspective. ICECS 2012: 905-908 - 2011
- [c24]Jucemar Monteiro, José Luís Güntzel, Luciano Volcan Agostini:
A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design. ICECS 2011: 442-445 - [c23]Vinicius S. Livramento, Bruno George de Moraes, Brunno Abner Machado, José Luís Güntzel:
An energy-efficient 8×8 2-D DCT VLSI architecture for battery-powered portable devices. ISCAS 2011: 587-590 - [c22]Vinicius S. Livramento, Bruno George de Moraes, Brunno Abner Machado, José Luís Almada Güntzel:
An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms. SBCCI 2011: 149-154 - [c21]Daniel P. Volpato, Alexandre Keunecke Ignácio Mendonça, José Luís Almada Güntzel, Luiz Cláudio Villar dos Santos:
Cache-tuning-aware scratchpad allocation from binaries. SBCCI 2011: 221-226 - 2010
- [c20]Daniel P. Volpato, Alexandre Keunecke Ignácio Mendonça, Luiz C. V. dos Santos, José Luís Almada Güntzel:
A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency. ISVLSI 2010: 127-132
2000 – 2009
- 2009
- [c19]Alexandre Keunecke Ignácio Mendonça, Daniel P. Volpato, José Luís Almada Güntzel, Luiz C. V. dos Santos:
Mapping Data and Code into Scratchpads from Relocatable Binaries. ISVLSI 2009: 157-162 - 2007
- [c18]Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel:
RIC Fast Adder and its Set Tolerant Implementation in FPGAs. FPL 2007: 638-641 - 2006
- [c17]Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Leandro Rosa, José Luís Güntzel, Ivan Saraiva Silva:
High throughput architecture for H.264/AVC forward transforms block. ACM Great Lakes Symposium on VLSI 2006: 320-323 - [c16]Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, José Luís Güntzel, Ivan Saraiva Silva, Sergio Bampi:
High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard. ISCAS 2006 - [c15]Daniel Lima Ferrão, Ricardo Reis, José Luís Almada Güntzel:
Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. PATMOS 2006: 301-310 - 2005
- [c14]Cristiano Santos, Daniel Lima Ferrão, Ricardo Reis, José Luís Güntzel:
Incremental timing optimization for automatic layout generation. ISCAS (4) 2005: 3567-3570 - 2004
- [c13]Ricardo Reis, Fernanda Lima Kastensmidt, José Luís Almada Güntzel:
Physical design methodologies for performance predictability and manufacturability. Conf. Computing Frontiers 2004: 390-397 - [c12]Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis:
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. PATMOS 2004: 732-741 - 2003
- [c11]David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán:
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS 2003: 501-510 - [c10]Daniel Lima Ferrão, Gustavo Wilke, Ricardo Augusto da Luz Reis, José Luís Almada Güntzel:
Improving Critical Path Identification in Functional Timing Analysis. SBCCI 2003: 297-302 - [c9]Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel:
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. SBCCI 2003: 303- - [c8]Cristiano Lazzari, Cristiano Viana Domingues, José Luís Almada Güntzel, Ricardo Augusto da Luz Reis:
A New Macro-cell Generation Strategy for three metal layer CMOS Technologies. VLSI-SOC 2003: 193-197 - [c7]Cristiano Lazzari, Cristiano Viana Domingues, José Luís Güntzel, Ricardo Reis:
A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits. VLSI-SoC (Selected Papers) 2003: 197-211 - 2002
- [c6]José Luís Güntzel, Gustavo Wilke, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis:
A Comparison Between Testability Measures Applied to Complex Gates. LATW 2002: 144-149 - [c5]Gustavo Wilke, José Luís Güntzel, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis:
Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing. SBCCI 2002: 277-282 - 2001
- [j1]José Luís Almada Güntzel, Ricardo Augusto da Luz Reis:
Análise de Timing Funcional de Circuitos VLSI Contendo Portas Complexas. RITA 8(1): 111-142 (2001) - [c4]José Luís Güntzel, Ana Cristina Medina Pinto, Ricardo Reis:
A Timed Calculus for ATG-Based Timing Analysis with Complex Gates. LATW 2001: 234-239 - 2000
- [c3]José Luís Güntzel, Ana Cristina Medina Pinto, Eduardo D'Avila, Ricardo Reis:
ATG-Based Timing Analysis of Circuits Containing Complex Gates. SBCCI 2000: 21-28
1990 – 1999
- 1999
- [c2]Fernanda Lima, Marcelo O. Johann, José Luís Almada Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Augusto da Luz Reis:
Designing a Mask Programmable Matrix for Sequential Circuits. VLSI 1999: 439-446 - 1998
- [c1]José Luís Güntzel, Ana Cristina Medina Pinto, Fernando Moraes, Ricardo Reis:
An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays. SBCCI 1998: 208-212
Coauthor Index
Vinicius S. Livramento
aka: Vinicius dos S. Livramento
aka: Vinicius dos S. Livramento
Luiz Cláudio Villar dos Santos
aka: Luiz C. V. dos Santos
aka: Luiz C. V. dos Santos
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last updated on 2024-03-11 23:29 CET by the dblp team
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