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2010 – today
- 2018
[j20]Leila Delshadtehrani, Schuyler Eldridge, Sadullah Canakci, Manuel Egele, Ajay Joshi:
Nile: A Programmable Monitoring Coprocessor. Computer Architecture Letters 17(1): 92-95 (2018)- [c42]Boyou Zhou, Anmol Gupta, Rasoul Jahanshahi, Manuel Egele, Ajay Joshi:
Hardware Performance Counters Can Detect Malware: Myth or Fact? AsiaCCS 2018: 457-468 - [c41]Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Saiful A. Mojumder, Tiansheng Zhang:
Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon. DATE 2018: 1441-1446 - 2017
- [j19]José L. Abellán, Ayse Kivilcim Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Cristian Morales, John Recchio, Vaishnav Srinivas, Tiansheng Zhang:
Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 36(5): 801-814 (2017) - [c40]Boyou Zhou, Manuel Egele, Ajay Joshi:
High-performance low-energy implementation of cryptographic algorithms on a programmable SoC for IoT devices. HPEC 2017: 1-6 - [i1]Zafar Takhirov, Joseph Wang, Marcia S. Louis, Venkatesh Saligrama, Ajay Joshi:
Field of Groves: An Energy-Efficient Random Forest. CoRR abs/1704.02978 (2017) - 2016
- [j18]José L. Abellán, Chao Chen, Ajay Joshi:
Electro-Photonic NoC Designs for Kilocore Systems. JETC 13(2): 24:1-24:25 (2016) - [j17]Amir Kavyan Ziabari, Yifan Sun, Yenai Ma, Dana Schaa, José L. Abellán, Rafael Ubal, John Kim, Ajay Joshi, David R. Kaeli:
UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs. TACO 13(4): 35:1-35:25 (2016) - [j16]Mahmoud Zangeneh, Ajay Joshi:
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization. IEEE Trans. VLSI Syst. 24(3): 884-896 (2016) - [c39]Ayse Kivilcim Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Yenai Ma, John Recchio, Vaishnav Srinivas, Tiansheng Zhang:
Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems. DATE 2016: 1309-1314 - [c38]Zafar Takhirov, Joseph Wang, Venkatesh Saligrama, Ajay Joshi:
Energy-Efficient Adaptive Classifier Design for Mobile Systems. ISLPED 2016: 52-57 - 2015
- [j15]Daniel Jovan Sooknanan, Ajay Joshi:
Using GUI Design Theory to Develop an Open Source Touchscreen Smartphone GUI. Computer and Information Science 8(2): 43-57 (2015) - [j14]Chao Chen, José L. Abellán, Ajay Joshi:
Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration. IEEE Trans. on CAD of Integrated Circuits and Systems 34(6): 972-985 (2015) - [c37]Schuyler Eldridge, Amos Waterland, Margo Seltzer, Jonathan Appavoo, Ajay Joshi:
Towards General-Purpose Neural Network Computing. PACT 2015: 99-112 - [c36]Boyou Zhou, Ronen Adato, Mahmoud Zangeneh, Tianyu Yang, Aydan Uyar, Bennett B. Goldberg, M. Selim Ünlü, Ajay Joshi:
Detecting hardware trojans using backside optical imaging of embedded watermarks. DAC 2015: 111:1-111:6 - [c35]T. Berkin Cilingiroglu, Mahmoud Zangeneh, Aydan Uyar, W. Clem Karl, Janusz Konrad, Ajay Joshi, Bennett B. Goldberg, M. Selim Ünlü:
Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits. DATE 2015: 597-600 - [c34]Amir Kavyan Ziabari, José L. Abellán, Rafael Ubal, Chao Chen, Ajay Joshi, David R. Kaeli:
Leveraging Silicon-Photonic NoC for Designing Scalable GPUs. ICS 2015: 273-282 - [c33]Amir Kavyan Ziabari, José L. Abellán, Yenai Ma, Ajay Joshi, David R. Kaeli:
Asymmetric NoC Architectures for GPU Systems. NOCS 2015: 25:1-25:8 - 2014
- [j13]Mahmoud Zangeneh, Ajay Joshi:
Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM. IEEE Trans. VLSI Syst. 22(8): 1815-1828 (2014) - [c32]Mahmoud Zangeneh, Ajay Joshi:
Sub-threshold logic circuit design using feedback equalization. DATE 2014: 1-6 - [c31]Tiansheng Zhang, José L. Abellán, Ajay Joshi, Ayse Kivilcim Coskun:
Thermal management of manycore systems with silicon-photonic networks. DATE 2014: 1-6 - [c30]Schuyler Eldridge, Florian Raudies, David Zou, Ajay Joshi:
Neural network-based accelerators for transcendental function approximation. ACM Great Lakes Symposium on VLSI 2014: 169-174 - [c29]Chao Chen, Tiansheng Zhang, Pietro Contu, Jonathan Klamkin, Ayse Kivilcim Coskun, Ajay Joshi:
Sharing and placement of on-chip laser sources in silicon-photonic NoCs. NOCS 2014: 88-95 - 2013
- [c28]Zafar Takhirov, Bobak Nazer, Ajay Joshi:
Energy-efficient pass-transistor-logic using decision feedback equalization. ISLPED 2013: 335-340 - 2012
- [j12]Christopher Batten, Ajay Joshi, Vladimir Stojanovic, Krste Asanovic:
Designing Chip-Level Nanophotonic Interconnection Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 137-153 (2012) - [j11]Zhen Wang, Mark G. Karpovsky, Ajay Joshi:
Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes. IEEE Trans. VLSI Syst. 20(6): 1036-1048 (2012) - [j10]Zhen Wang, Mark G. Karpovsky, Ajay Joshi:
Nonlinear Multi-Error Correction Codes for Reliable MLC nand Flash Memories. IEEE Trans. VLSI Syst. 20(7): 1221-1234 (2012) - [c27]Mahmoud Zangeneh, Ajay Joshi:
Performance and energy models for memristor-based 1T1R RRAM cell. ACM Great Lakes Symposium on VLSI 2012: 9-14 - [c26]Ajay Joshi, Chao Chen, Zafar Takhirov, Bobak Nazer:
A multi-layer approach to green computing: Designing energy-efficient digital circuits and manycore architectures. IGCC 2012: 1-3 - [c25]Zafar Takhirov, Bobak Nazer, Ajay Joshi:
Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit. ISQED 2012: 312-319 - [c24]Ajay Joshi:
Tutorial T8A: Designing Silicon-Photonic Communication Networks for Manycore Systems. VLSI Design 2012: 28 - 2011
- [c23]Zafar Takhirov, Bobak Nazer, Ajay Joshi:
A preliminary look at error avoidance in digital logic via feedback equalization. Allerton 2011: 1390-1391 - [c22]Jie Meng, Chao Chen, Ayse Kivilcim Coskun, Ajay Joshi:
Run-time energy management of manycore systems through reconfigurable interconnects. ACM Great Lakes Symposium on VLSI 2011: 43-48 - [c21]Zhen Wang, Mark G. Karpovsky, Ajay Joshi:
Influence of metallic tubes on the reliability of CNTFET SRAMs: error mechanisms and countermeasures. ACM Great Lakes Symposium on VLSI 2011: 359-362 - [c20]Chao Chen, Jie Meng, Ayse Kivilcim Coskun, Ajay Joshi:
Express Virtual Channels with Taps (EVC-T): A Flow Control Technique for Network-on-Chip (NoC) in Manycore Systems. Hot Interconnects 2011: 1-10 - 2010
- [c19]Zhen Wang, Mark G. Karpovsky, Ajay Joshi:
Reliable MLC NAND flash memories based on nonlinear t-error-correcting codes. DSN 2010: 41-50 - [c18]Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic:
Re-architecting DRAM memory systems with monolithically integrated silicon photonics. ISCA 2010: 129-140
2000 – 2009
- 2009
- [j9]Christopher Batten, Ajay Joshi, Jason Orcutt, Anatol Khilo, Benjamin Moss, Charles Holzwarth, Milos A. Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic:
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics. IEEE Micro 29(4): 8-21 (2009) - [c17]Ajay Joshi, Byungsub Kim, Vladimir Stojanovic:
Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects. Hot Interconnects 2009: 3-12 - [c16]Zhen Wang, Mark G. Karpovsky, Berk Sunar, Ajay Joshi:
Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes. ICICS 2009: 47-62 - [c15]Scott Beamer, Krste Asanovic, Christopher Batten, Ajay Joshi, Vladimir Stojanovic:
Designing multi-socket systems using silicon photonics. ICS 2009: 521-522 - [c14]Ajay Joshi, Fred Chen, Vladimir Stojanovic:
A Modeling and exploration framework for interconnect network design in the nanometer era. NOCS 2009: 91 - [c13]Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanovic, Vladimir Stojanovic:
Silicon-photonic clos networks for global on-chip communication. NOCS 2009: 124-133 - 2008
- [j8]Nitesh V. Chawla, David A. Cieslak, Lawrence O. Hall, Ajay Joshi:
Automatically countering imbalance and its empirical relationship to cost. Data Min. Knowl. Discov. 17(2): 225-252 (2008) - [j7]Yue Luo, Ajay Joshi, Aashish Phansalkar, Lizy Kurian John, Joydeep Ghosh:
Analysing and improving clustering based sampling for microprocessor simulation. IJHPCN 5(4): 200-214 (2008) - [j6]Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John:
Distilling the essence of proprietary workloads into miniature benchmarks. TACO 5(2): 10:1-10:33 (2008) - [c12]Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos A. Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic:
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. Hot Interconnects 2008: 21-30 - 2007
- [j5]Aashish Phansalkar, Ajay Joshi, Lizy K. John:
Subsetting the SPEC CPU2006 benchmark suite. SIGARCH Computer Architecture News 35(1): 69-76 (2007) - [j4]Ajay Joshi, Yue Luo, Lizy K. John:
Applying Statistical Sampling for Fast and Efficient Simulation of Commercial Workloads. IEEE Trans. Computers 56(11): 1520-1533 (2007) - [j3]Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis:
Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. IEEE Trans. VLSI Syst. 15(9): 990-1002 (2007) - [c11]Aashish Phansalkar, Ajay Joshi, Lizy Kurian John:
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite. ISCA 2007: 412-423 - [c10]Fred Chen, Ajay Joshi, Vladimir Stojanovic, Anantha Chandrakasan:
Scaling and evaluation of carbon nanotube interconnects for VLSI applications. Nano-Net 2007: 24 - 2006
- [j2]Ajay Joshi, Aashish Phansalkar, Lieven Eeckhout, Lizy Kurian John:
Measuring Benchmark Similarity Using Inherent Program Characteristics. IEEE Trans. Computers 55(6): 769-782 (2006) - [c9]Joshua J. Yi, Resit Sendag, Lieven Eeckhout, Ajay Joshi, David J. Lilja, Lizy Kurian John:
Evaluating Benchmark Subsetting Approaches. IISWC 2006: 93-104 - [c8]Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John:
Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks. IISWC 2006: 105-115 - [c7]Ajay Joshi, Joshua J. Yi, Robert H. Bell Jr., Lieven Eeckhout, Lizy Kurian John, David J. Lilja:
Evaluating the efficacy of statistical simulation for design space exploration. ISPASS 2006: 70-79 - [c6]Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis:
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing. VLSI Design 2006: 773-776 - 2005
- [j1]Ajay Joshi, Jeffrey A. Davis:
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI). IEEE Trans. VLSI Syst. 13(8): 899-910 (2005) - [c5]Ajay Joshi, Jeffrey A. Davis:
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. ACM Great Lakes Symposium on VLSI 2005: 446-451 - [c4]Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout, Lizy Kurian John:
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites. ISPASS 2005: 10-20 - [c3]Yue Luo, Ajay Joshi, Aashish Phansalkar, Lizy Kurian John, Joydeep Ghosh:
Analyzing and Improving Clustering Based Sampling for Microprocessor Simulation. SBAC-PAD 2005: 193-200 - [c2]Ajay Joshi, Jeffrey A. Davis:
Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing. SoCC 2005: 137-142 - 2004
- [c1]Ajay Joshi, Jeffrey A. Davis:
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). SLIP 2004: 64-68
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