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ORCIDSudeendra Kumar K
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2020 – today
- 2023
[j6]Preethi
, Mohan Govindsa Kabadi, Sudeendra Kumar K, K. K. Mahapatra:
Sorter Design with Structured Low Power Techniques. SN Comput. Sci. 4(2): 129 (2023)- [c21]Sudeendra Kumar K, S. S. Rekha, Akshay Koushik, Ayas Kanta Swain, K. K. Mahapatra:
Lightweight Secured Split Test Technique with RMA Capability to Prevent IC Counterfeiting. iSES 2023: 191-196 - 2022
- [c20]Magna Mishra, Sudeendra Kumar K, Ayas Kanta Swain, Kamala Kanta Mahapatra:
PUF Based Authentication System for IoT Nodes: A Comparative Study. iSES 2022: 390-393 - 2021
- [c19]Preethi, Mohan Govindsa Kabadi, K. Sudeendra Kumar, K. K. Mahapatra:
Low Power Sorters Using Clock Gating. iSES 2021: 6-11 - [c18]S. S. Rekha, K. Suraj, K. Sudeendra Kumar:
A Holistic Blockchain Based IC Traceability Technique. iSES 2021: 307-310
2010 – 2019
- 2019
- [j5]Sudeendra Kumar K, Naini Satheesh, Abhishek Mahapatra, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
Physical Unclonable Functions for On-Chip Instrumentation: Enhancing the Security of the Internal Joint Test Action Group Network. IEEE Consumer Electron. Mag. 8(4): 62-66 (2019) - 2018
- [j4]Sauvagya Ranjan Sahoo, Sudeendra Kumar K, Kamalakanta Mahapatra:
A novel configurable ring oscillator PUF with improved reliability using reduced supply voltage. Microprocess. Microsystems 60: 40-52 (2018) - [c17]Saswat Kumar Ram, Sauvagya Ranjan Sahoo, Sudeendra Kumar K, Kamalakanta Mahapatra:
Energy Efficient Ultra Low Power Solar Harvesting System Design with MPPT for IOT Edge Node Devices. iSES 2018: 130-133 - [c16]Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Krishna Kiran, Ayas Kanta Swain, Kamala Kanta Mahapatra:
A Novel Holistic Security Framework for In-Field Firmware Updates. iSES 2018: 261-264 - [c15]Sudeendra Kumar K, Saurabh Seth, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamalakanta Mahapatra:
PUF-Based Secure Test Wrapper for SoC Testing. ISVLSI 2018: 672-677 - [c14]Manoj Kumar JYV, Ayas Kanta Swain, Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Kamalakanta Mahapatra:
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip. ISVLSI 2018: 738-743 - 2017
- [j3]K. Sudeendra Kumar, G. Hanumanta Rao, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
Secure split test techniques to prevent IC piracy for IoT devices. Integr. 58: 390-400 (2017) - [j2]Sauvagya Ranjan Sahoo, K. Sudeendra Kumar, Kamalakanta Mahapatra:
A novel current controlled configurable RO PUF with improved security metrics. Integr. 58: 401-410 (2017) - [c13]Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra:
Security Enhancements to System on Chip Devices for IoT Perception Layer. iNIS 2017: 151-156 - [c12]Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra:
Microprocessor Based Physical Unclonable Function. iNIS 2017: 246-251 - [c11]Sauvagya Ranjan Sahoo, Sudeendra Kumar K, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra:
On-chip RO-Sensor for Recycled IC Detection. iNIS 2017: 252-256 - [c10]Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra:
Analysis of Side-Channel Attack AES Hardware Trojan Benchmarks against Countermeasures. ISVLSI 2017: 574-579 - [c9]K. Sudeendra Kumar, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra:
A Flexible Pay-per-Device Licensing Scheme for FPGA IP Cores. ISVLSI 2017: 677-682 - 2016
- [j1]Govinda Rao Locharla, K. Sudeendra Kumar, Kamala Kanta Mahapatra, Samit Ari:
Implementation of MIMO data reordering and scheduling methodologies for eight-parallel variable length multi-path delay commutator FFT/IFFT. IET Comput. Digit. Tech. 10(5): 215-225 (2016) - [c8]Sudeendra Kumar K, Naini Satheesh, Abhishek Mahapatra, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
Securing IEEE 1687 Standard On-chip Instrumentation Access Using PUF. iNIS 2016: 56-61 - [c7]Naini Satheesh, Abhishek Mahapatra, Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
A Modified RO-PUF with Improved Security Metrics on FPGA. iNIS 2016: 178-181 - [c6]Sauvagya Ranjan Sahoo, K. Sudeendra Kumar, Kamalakanta Mahapatra, Ayas Kanta Swain:
A Novel Aging Tolerant RO-PUF for Low Power Application. iNIS 2016: 187-192 - 2015
- [c5]K. Sudeendra Kumar, G. Hanumantha Rao, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
A Novel PUF Based SST to Prevent Distribution of Rejected ICs from Untrusted Assembly. iNIS 2015: 314-319 - [c4]Sauvagya Ranjan Sahoo, K. Sudeendra Kumar, Kamalakanta Mahapatra:
A Modified Configurable RO PUF with Improved Security Metrics. iNIS 2015: 320-324 - [c3]K. Sudeendra Kumar, Rakesh Chanamala, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
An improved AES Hardware Trojan benchmark to validate Trojan detection schemes in an ASIC design flow. VDAT 2015: 1-6 - [c2]Govinda Rao Locharla, K. Sudeendra Kumar, Kamala Kanta Mahapatra, Samit Ari:
Implementation of input data buffering and scheduling methodology for 8 parallel MDC FFT. VDAT 2015: 1-6 - [c1]Sauvagya Ranjan Sahoo, K. Sudeendra Kumar, Kamalakanta Mahapatra:
A novel ROPUF for hardware security. VDAT 2015: 1-2
Coauthor Index
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