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ORCIDC. L. Liu 0001
Chung Laung (Dave) Liu – 劉炯朗
Person information
- unicode name: 劉炯朗
- affiliation: National Cheng Kung University, Tainan, Taiwan
- affiliation (former): National Tsing Hua University, Hsinchu, Taiwan
- award (1994): IEEE James H. Mulligan, Jr. Education Medal
Other persons with the same name
- C. L. Liu 0002 — East China University of Science and Technology, Shanghai, China
- C. L. Liu 0003 — Shandong University, Department of Physics, Jinan, China
- C. L. Liu 0004 — Hebei University of Technology, School of Mechanical Engineering, Tianjin, China
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2010 – 2019
- 2012
[c78]C. L. Liu:
I attended the nineteenth design automation conference. ISPD 2012: 69-70
2000 – 2009
- 2005
- [c77]C. L. Liu:
The High Walls have Crumpled. VLSI Design 2005: 21-24 - 2003
- [j63]Ali Pinar, C. L. Liu:
Compacting sequences with invariant transition frequencies. ACM Trans. Design Autom. Electr. Syst. 8(2): 214-221 (2003) - [j62]Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 79-89 (2003) - [j61]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang:
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 879-887 (2003) - 2002
- [j60]Ki-Seok Chung, Taewhan Kim, C. L. Liu:
A Complete Model for Glitch Analysis in Logic Circuits. J. Circuits Syst. Comput. 11(2): 137-154 (2002) - [j59]Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang:
Domino logic synthesis based on implication graph. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 232-240 (2002) - [j58]Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu:
Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002) - [j57]Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu:
Synthesis and Optimization of Combinational Interface Circuits. J. VLSI Signal Process. 31(3): 243-261 (2002) - [c76]S. L. Lung, Dennis Lin, S. S. Chen, Gary Weng, C. L. Liu, S. C. Lai, C. W. Tsai, T. B. Wu, Rich Liu:
Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application. CICC 2002: 479-482 - [c75]Shih-Liang Chen, TingTing Hwang, C. L. Liu:
A technology mapping algorithm for CPLD architectures. FPT 2002: 204-210 - 2001
- [j56]Prashant Saxena, C. L. Liu:
Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 503-515 (2001) - [j55]Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Architecture driven circuit partitioning. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 383-389 (2001) - [j54]Ki-Seok Chung, Taewhan Kim, C. L. Liu:
G-vector: A New Model for Glitch Analysis in Logic Circuits. J. VLSI Signal Process. 27(3): 235-251 (2001) - [c74]Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang:
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737 - [c73]Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu:
Binary decision diagram with minimum expected path length. DATE 2001: 708-712 - 2000
- [j53]Prashant Saxena, C. L. Liu:
A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6): 691-702 (2000) - [j52]Chaeryung Park, Taewhan Kim, C. L. Liu:
An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. VLSI Design 11(4): 381-396 (2000) - [c72]Junhyung Um, Taewhan Kim, C. L. Liu:
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. DAC 2000: 98-103 - [c71]Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang:
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321 - [c70]Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
Noise-aware power optimization for on-chip interconnect. ISLPED 2000: 108-113
1990 – 1999
- 1999
- [j51]Peichen Pan, C. L. Liu:
Partial Scan with Preselected Scan Signals. IEEE Trans. Computers 48(9): 1000-1005 (1999) - [c69]Prashant Saxena, C. L. Liu:
Crosstalk Minimization Using Wire Perturbations. DAC 1999: 100-103 - [c68]Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu:
Logic Transformation for Low Power Synthesis. DATE 1999: 158-162 - [c67]Ki-Wook Kim, C. L. Liu, Sung-Mo Kang:
Implication graph based domino logic synthesis. ICCAD 1999: 111-114 - [c66]Junhyung Um, Taewhan Kim, C. L. Liu:
Optimal allocation of carry-save-adders in arithmetic optimization. ICCAD 1999: 410-413 - [c65]Chaeryung Park, Taewhan Park, C. L. Liu:
An efficient data path synthesis algorithm for behavioral-level power optimization. ISCAS (1) 1999: 294-297 - [c64]C. L. Liu:
From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years. RTSS 1999: 5 - [c63]Prashant Saxena, Peichen Pan, C. L. Liu:
The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design 1999: 402-407 - 1998
- [j50]Peichen Pan, Arvind K. Karandikar, C. L. Liu:
Optimal clock period clustering for sequential circuits with retiming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6): 489-498 (1998) - [j49]Peichen Pan, C. L. Liu:
Optimal clock period FPGA technology mapping for sequential circuits. ACM Trans. Design Autom. Electr. Syst. 3(3): 437-462 (1998) - [j48]Chaeryung Park, Taewhan Kim, C. L. Liu:
Register Allocation - A Hierarchical Reduction Approach. J. VLSI Signal Process. 19(3): 269-285 (1998) - [c62]Prashant Saxena, C. L. Liu:
A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD 1998: 124-127 - [c61]Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Architecture driven circuit partitioning. ICCAD 1998: 408-411 - [c60]Ali Pinar, C. L. Liu:
Power invariant vector sequence compaction. ICCAD 1998: 473-476 - [c59]Unni Narayanan, Peichen Pan, C. L. Liu:
Low power logic synthesis under a general delay model. ISLPED 1998: 209-214 - [c58]Ki-Seok Chung, C. L. Liu:
Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. ISLPED 1998: 215-220 - 1997
- [j47]Peichen Pan, Sai-keung Dong, C. L. Liu:
Optimal Graph Constraint Reduction for Symbolic Layout Compaction. Algorithmica 18(4): 560-574 (1997) - [j46]Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu:
Routing for symmetric FPGAs and FPICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 20-31 (1997) - [j45]Anmol Mathur, C. L. Liu:
Timing-driven placement for regular architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6): 597-608 (1997) - [c57]Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Low Power FPGA Design - A Re-engineering Approach. DAC 1997: 656-661 - [c56]Unni Narayanan, C. L. Liu:
Low power logic synthesis for XOR based circuits. ICCAD 1997: 570-574 - [c55]Arvind K. Karandikar, Peichen Pan, C. L. Liu:
Optimal Clock Period Clustering for Sequential Circuits with Retiming. ICCD 1997: 122-127 - 1996
- [j44]Peichen Pan, Weiping Shi, C. L. Liu:
Area Minimization for Hierarchical Floorplans. Algorithmica 15(6): 550-571 (1996) - [j43]Tong Gao, C. L. Liu:
Minimum crosstalk channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 465-474 (1996) - [j42]Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu:
Low power realization of finite state machines - a decomposition approach. ACM Trans. Design Autom. Electr. Syst. 1(3): 315-340 (1996) - [j41]Srilata Raman, C. L. Liu, Larry G. Jones:
Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation. VLSI Design 4(4): 345-355 (1996) - [j40]Taewhan Kim, C. L. Liu:
An integrated algorithm for incremental data path synthesis. J. VLSI Signal Process. 12(3): 265-285 (1996) - [c54]Peichen Pan, C. L. Liu:
Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. DAC 1996: 720-725 - [c53]Xiangfeng Chen, Peichen Pan, C. L. Liu:
Desensitization for Power Reduction in Sequential Circuits. DAC 1996: 795-800 - [c52]Anmol Mathur
, C. L. Liu:
Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs. ED&TC 1996: 165-169 - [c51]Srilata Raman, C. L. Liu, Larry G. Jones:
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs. ED&TC 1996: 170-175 - [c50]Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu:
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831 - [c49]Peichen Pan, C. L. Liu:
Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. FPGA 1996: 58-64 - [c48]Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu:
An algorithm for synthesis of system-level interface circuits. ICCAD 1996: 442-447 - 1995
- [j39]Taewhan Kim, C. L. Liu:
A new approach to the multiport memory allocation problem in data path synthesis. Integr. 19(3): 133-160 (1995) - [j38]Tong Gao, C. L. Liu:
Minimum crosstalk switchbox routing. Integr. 19(3): 161-180 (1995) - [j37]Peichen Pan, C. L. Liu:
Area minimization for floorplans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1): 123-132 (1995) - [j36]Ran Libeskind-Hadas, Nimish Shrivastava, Rami G. Melhem, C. L. Liu:
Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays. IEEE Trans. Parallel Distributed Syst. 6(5): 498-511 (1995) - [c47]Peichen Pan, C. L. Liu:
Partial Scan with Pre-selected Scan Signals. DAC 1995: 189-194 - [c46]Anmol Mathur, Kuang-Chien Chen, C. L. Liu:
Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. FPGA 1995: 118-124 - [c45]Anmol Mathur, Kuang-Chien Chen, C. L. Liu:
Re-engineering of timing constrained placements for regular architectures. ICCAD 1995: 485-490 - 1994
- [j35]Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu:
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 425-438 (1994) - [c44]Yachyang Sun, C. L. Liu:
Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. DAC 1994: 171-176 - [c43]Srilata Raman, C. L. Liu, Larry G. Jones:
A delay driven FPGA placement algorithm. EURO-DAC 1994: 277-282 - [c42]Anmol Mathur, C. L. Liu:
Compression-relaxation: a new approach to performance driven placement for regular architectures. ICCAD 1994: 130-136 - [c41]Peichen Pan, Weiping Shi, C. L. Liu:
Area minimization for hierarchical floorplans. ICCAD 1994: 436-440 - [c40]Tong Gao, C. L. Liu:
Minimum crosstalk switchbox routing. ICCAD 1994: 610-615 - 1993
- [j34]Jason Cong, Bryan Preas, C. L. Liu:
Physical models and efficient algorithms for over-the-cell routing in standard cell design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 723-734 (1993) - [j33]Wei-Kuan Shih, Jane W.-S. Liu, C. L. Liu:
Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines. IEEE Trans. Software Eng. 19(12): 1171-1179 (1993) - [c39]Taewhan Kim, C. L. Liu:
Utilization of Multiport Memories in Data Path Synthesis. DAC 1993: 298-302 - [c38]Peichen Pan, Sai-keung Dong, C. L. Liu:
Optimal Graph Constraint Reduction for Symbolic Layout Compaction. DAC 1993: 401-406 - [c37]Tong Gao, Chung Laung (Dave) Liu, Kuang-Chien Chen:
A performance driven hierarchical partitioning placement algorithm. EURO-DAC 1993: 33-38 - [c36]Chaeryung Park, Taewhan Kim, C. L. Liu:
Register allocation for data flow graphs with conditional branches and loops. EURO-DAC 1993: 232-237 - [c35]Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu:
Routing for symmetric FPGAs and FPICs. ICCAD 1993: 486-490 - [c34]Tong Gao, C. L. Liu:
Minimum crosstalk channel routing. ICCAD 1993: 692-696 - 1992
- [c33]Tong Gao, Pravin M. Vaidya, C. L. Liu:
A Performance Driven Macro-Cell Placement Algorithm. DAC 1992: 147-152 - [c32]Peichen Pan, C. L. Liu:
Area minimization for general floorplans. ICCAD 1992: 606-609 - [c31]Yachyang Sun, C. L. Liu:
An Area Minimizer for Floorplans with L-Shaped Regions. ICCD 1992: 383-386 - [c30]C. L. Liu:
Fundamentals of Real-Time Scheduling (Extended Abstract). NATO ASI RTC 1992: 1-7 - 1991
- [j32]Nany Hasan, C. L. Liu:
Minimum fault covering in reconfigurable arrays. Integr. 11(3): 215-234 (1991) - [j31]Philip K. McKinley, Nany Hasan, Ran Libeskind-Hadas, C. L. Liu:
Disjoint Covers in Replicated Heterogeneous Arrays. SIAM J. Discret. Math. 4(2): 281-292 (1991) - [j30]Jason Cong, C. L. Liu:
On the k-layer planar subset and topological via minimization problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 972-981 (1991) - [c29]Tong Gao, Pravo M. Vaidya, C. L. Liu:
A New Performance Driven Placement Algorithm. ICCAD 1991: 44-47 - [c28]Taewhan Kim, Jane W.-S. Liu, C. L. Liu:
A Scheduling Algorithm for Conditional Resource Sharing. ICCAD 1991: 84-87 - [c27]Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu:
A Channel Router for Single Layer Customization Technology. ICCAD 1991: 436-439 - 1990
- [j29]Xianjin Yao, C. L. Liu:
PLA logic minimization by simulated annealing. Integr. 9(3): 243-257 (1990) - [j28]Jason Cong, C. L. Liu:
Over-the-cell channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 408-418 (1990) - [c26]Jason Cong, Bryan Preas, C. L. Liu:
General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. DAC 1990: 709-715 - [c25]Jason Cong, C. L. Liu:
On the k-layer planar subset and via minimization problems. EURO-DAC 1990: 459-463 - [c24]Xianjin Yao, C. L. Liu:
Solution of a module orientation and rotation problem. EURO-DAC 1990: 584-588 - [c23]Nany Hasan, C. L. Liu:
Fault covers in reconfigurable PLAs. FTCS 1990: 166-173
1980 – 1989
- 1989
- [j27]D. F. Wong, C. L. Liu:
Floorplan Design of VLSI Circuits. Algorithmica 4(2): 263-291 (1989) - [j26]Xiaojun Shen, Y. Z. Cai, C. L. Liu, Clyde P. Kruskal:
Generalized latin squares I. Discret. Appl. Math. 25(1-2): 155-178 (1989) - [j25]Thomas R. Mueller, D. F. Wong, C. L. Liu:
An enhanced bottom-up algorithm for floorplan design. Integr. 7(2): 189-201 (1989) - [j24]Xianjin Yao, Masaaki Yamada, C. L. Liu:
A new approach to the pin assignment problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(9): 999-1006 (1989) - [c22]Ran Libeskind-Hadas, C. L. Liu:
Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. DAC 1989: 400-405 - [c21]Sai-keung Dong, Jason Cong, C. L. Liu:
Constrained floorplan design for flexible blocks. ICCAD 1989: 488-491 - 1988
- [j23]Jason Cong, Martin D. F. Wong, C. L. Liu:
A new approach to three- or four-layer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10): 1094-1104 (1988) - [c20]Xianji Yao, Masaaki Yamada, C. L. Liu:
A New Approach to the Pin Assignment Problem. DAC 1988: 566-572 - [c19]Nany Hasan, C. L. Liu:
Minimum fault coverage in reconfigurable arrays. FTCS 1988: 348-353 - [c18]Jingsheng Cong, C. L. Liu:
Over-the-cell channel routing. ICCAD 1988: 80-83 - [c17]Nany Hasan, Jason Cong, C. L. Liu:
A new formulation of yield enhancement problems for reconfigurable chips. ICCAD 1988: 520-523 - 1987
- [j22]H. W. Leong, C. L. Liu:
Algorithms for permutation channel routing. Integr. 5(1): 17-45 (1987) - [c16]D. F. Wong, C. L. Liu:
Array Optimization for VLSI Synthesis. DAC 1987: 537-543 - 1986
- [j21]D. F. Wong, C. L. Liu:
Compacted channel routing with via placement restrictions. Integr. 4(4): 287-307 (1986) - [j20]J. L. Lewandowski, C. L. Liu, Jane W.-S. Liu:
An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem. J. Algorithms 7(3): 323-330 (1986) - [c15]D. F. Wong, C. L. Liu:
A new algorithm for floorplan design. DAC 1986: 101-107 - 1985
- [j19]Prakash V. Ramanan, C. L. Liu:
Permutation Representation of k-Ary Trees. Theor. Comput. Sci. 38: 83-98 (1985) - 1984
- [j18]Prakash V. Ramanan, Jitender S. Deogun, C. L. Liu:
A Personnel Assignment Problem. J. Algorithms 5(1): 132-144 (1984) - [j17]Jack R. Egan, C. L. Liu:
Bipartite Folding and Partitioning of a PLA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(3): 191-199 (1984) - [c14]J. L. Lewandowski, C. L. Liu:
A branch and bound algorithm for optimal pla folding. DAC 1984: 426-433 - 1983
- [j16]W.-D. Wei, C. L. Liu:
On a Periodic Maintenance Problem. Oper. Res. Lett. 2(2): 90-93 (1983) - [j15]J. L. Lewandowski, Jane W.-S. Liu, C. L. Liu:
SS/TDMA Time Slot Assignment with Restricted Switching Modes. IEEE Trans. Commun. 31(1): 149-154 (1983) - [j14]D. T. Lee, C. L. Liu, C. K. Wong:
(g 0, g 1, ... g k)-Trees and Unary OL Systems. Theor. Comput. Sci. 22: 209-217 (1983) - [c13]Hon Wai Leong, C. L. Liu:
A new channel routing problem. DAC 1983: 584-590 - 1982
- [j13]C. L. Liu, Jane W.-S. Liu, Arthur L. Liestman:
Scheduling with Slack Time. Acta Informatica 17: 31-41 (1982) - [c12]Jack R. Egan, C. L. Liu:
Optimal bipartite folding of PLA. DAC 1982: 141-146 - 1980
- [c11]C. L. Liu:
Generation of trees. CLAAP 1980: 45-53
1970 – 1979
- 1978
- [j12]Jane W.-S. Liu, C. L. Liu:
Performance Analysis of Multiprocessor Systems Containing Functionally Dedicated Processors. Acta Informatica 10: 95-104 (1978) - [j11]K. M. Chung, C. L. Liu:
A generalization of Ramsey theory for graphs. Discret. Math. 21(2): 117-127 (1978) - [j10]Sudarshan K. Dhall, C. L. Liu:
On a Real-Time Scheduling Problem. Oper. Res. 26(1): 127-140 (1978) - 1976
- [c10]C. L. Liu:
Deterministic Job Scheduling in Computing Systems. Performance 1976: 241-254 - 1975
- [j9]C. L. Liu:
Sperner's theorem on maximal-sized antichains and its generalization. Discret. Math. 11(2): 133-139 (1975) - 1974
- [c9]Jane W.-S. Liu, C. L. Liu:
Bounds on Scheduling Algorithms for Heterogeneous Comnputing Systems. IFIP Congress 1974: 349-353 - [c8]N. F. Chen, C. L. Liu:
On a Class of Scheduling Algorithms for Multiprocessors Computing Systems. Sagamore Computer Conference 1974: 1-16 - 1973
- [j8]C. L. Liu, B. G. Ong, Gregory R. Ruth:
A construction scheme for linear and non-linear codes. Discret. Math. 4(2): 171-184 (1973) - [j7]C. L. Liu, James W. Layland:
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. J. ACM 20(1): 46-61 (1973) - [c7]C. L. Liu:
Analysis of sorting algorithms. AFIPS National Computer Conference 1973: 453 - [c6]C. K. Wong, C. L. Liu, J. Apter:
A drum scheduling algorithm. Automatentheorie und Formale Sprachen 1973: 267-275 - 1972
- [j6]C. L. Liu:
Analysis and Synthesis of Sorting Algorithms. SIAM J. Comput. 1(4): 290-304 (1972) - [j5]Chin-Chong Tseng, C. L. Liu:
Complementary sets of sequences. IEEE Trans. Inf. Theory 18(5): 644-652 (1972) - [c5]C. L. Liu:
Optimal Scheduling on Multi-Processor Computing Systems. SWAT 1972: 155-160 - 1971
- [c4]C. L. Liu:
Analysis of Sorting Algorithms. SWAT 1971: 207-215
1960 – 1969
- 1969
- [j4]C. L. Liu:
A Note on Definite Stochastic Sequential Machines. Inf. Control. 14(4): 407-421 (1969) - [j3]C. L. Liu:
Lattice Functions, Pair Algebras, and Finite-State Machines. J. ACM 16(3): 442-454 (1969) - 1967
- [c3]C. L. Liu, G. D. Chang, R. E. Marks:
The design and implementation of a table driven compiler system. AFIPS Spring Joint Computing Conference 1967: 691-697 - 1966
- [j2]C. L. Liu:
Some algebraic properties of multi-threshold functions. IEEE Trans. Electron. Comput. 15(6): 935-938 (1966) - [c2]C. L. Liu:
Pair Algebra and Its Application. SWAT 1966: 103-112 - 1964
- [j1]C. L. Liu:
kth-Order Finite Automaton. IEEE Trans. Electron. Comput. 13(5): 642 (1964) - [c1]C. L. Liu:
Sequential-machine realization using feedback shift registers. SWCT 1964: 209-227
Coauthor Index
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