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Vinod Menezes
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2020 – today
- 2022
- [c13]Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu:
A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture. ICECS 2022 2022: 1-4 - 2021
- [c12]Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha P. Chandrakasan:
150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. VLSID 2021: 169-174
2010 – 2019
- 2019
- [j3]Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan:
Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting. IEEE J. Solid State Circuits 54(9): 2590-2600 (2019) - [j2]Kishalay Datta, Vinod Menezes, Shanthi Pavan:
Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 3227-3237 (2019) - 2018
- [c11]Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan:
Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting. ESSCIRC 2018: 42-45 - [c10]R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale:
A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. VLSID 2018: 171-176 - 2015
- [c9]Vipul Kumar Singhal, Vinod Menezes, Srinivasa Chakravarthy, Mahesh Mehendale:
8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process. ISSCC 2015: 1-3 - 2013
- [c8]Rashmi Sachan, Shahid Ali, Chandan Bist, Sunil Misra, Vinod Menezes, Sharad Gupta, Pat Bosshart:
A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture. VLSI Design 2013: 55-59 - 2011
- [c7]Michael Clinton, Clive Bittlestone, G. Girishankar, Viet Le, Vinod Menezes:
Design and technology interaction beyond 32nm. CICC 2011: 1-9
2000 – 2009
- 2009
- [c6]Karthik Rajagopal, Aatmesh, Vinod Menezes:
An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process. ISQED 2009: 103-106 - 2008
- [c5]Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H. M. Roopashree:
A Robust Level-Shifter Design for Adaptive Voltage Scaling. VLSI Design 2008: 383-388 - 2007
- [c4]Rachit Kumar Gupta, Vikas Narang, H. M. Roopashree, Vinod Menezes:
A low-power 333Mbps mobile-double data rate output driver with adaptive feedback to minimize overshoots and undershoots. ACM Great Lakes Symposium on VLSI 2007: 477-480 - 2005
- [c3]Rajat Chauhan, Karthik Rajagopal, Vinod Menezes, H. M. Roopashree, Sanish Koshy Jacob:
A high performance, high voltage output buffer in a low voltage CMOS process. CICC 2005: 227-230 - 2003
- [c2]Vinod Menezes, C. B. Keshav, Sushil Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau:
Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node. VLSI Design 2003: 122-127
1990 – 1999
- 1997
- [j1]Vinod Menezes, S. K. Nandy, Biswadip Mitra:
Signal compression through spatial frequency-based motion estimation. Integr. 22(1-2): 115-135 (1997) - 1996
- [c1]Vinod Menezes, Soumitra Kumar Nandy, Biswadip Mitra:
Spatial frequency based motion estimation for image sequence compression. HiPC 1996: 257-262
Coauthor Index
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