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Subir K. Roy
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2010 – 2019
- 2016
- [c13]Ambuj Mishra, Subir K. Roy:
Formal verification of switched capacitor DC to DC power converter using circuit simulation traces. VDAT 2016: 1-2 - [c12]Pavan Kumar Nadimpalli, Subir K. Roy:
An efficient FPGA-based function profiler for embedded system applications. VDAT 2016: 1-6 - 2013
- [j2]Kusum Lata, Subir K. Roy:
Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces. J. Electron. Test. 29(5): 715-740 (2013) - 2010
- [c11]Lopamudra Sen, Amit Roy, Supriya Bhattacharjee, Bijitendra Mittra, Subir K. Roy:
DFT logic verification through property based formal methods - SOC to IP. FMCAD 2010: 33
2000 – 2009
- 2008
- [c10]Sukumar Jairam, Kusum Lata, Subir K. Roy, Navakanta Bhat:
Verification of a MEMS based adaptive cruise control system using simulation and semi-formal approaches. ICECS 2008: 910-913 - 2007
- [c9]Subir K. Roy:
Top Level SOC Interconnectivity Verification Using Formal Techniques. MTV 2007: 63-70 - [c8]Subir K. Roy, Rubin A. Parekhji:
Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. VLSI Design 2007: 364-372 - 2002
- [c7]Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan:
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). ASP-DAC/VLSI Design 2002: 11-13 - 2000
- [c6]Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata:
Formal verification based on assume and guarantee approach - a case study (short paper). ASP-DAC 2000: 77-80 - [c5]Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata:
Dataflow Analysis for Resource Contention and Register Leakage Properties. VLSI Design 2000: 418-423
1990 – 1999
- 1999
- [c4]Bupesh Pandita, Subir K. Roy:
Design and Implementation of Viterbi Decoder Using FPGAs. VLSI Design 1999: 611- - [c3]Pradip K. Kar, Subir K. Roy:
TECHMIG: A Layout Tool for Technology Migration. VLSI Design 1999: 615-620 - 1996
- [j1]H. Narayanan, Subir K. Roy, Sachin B. Patkar:
Approximation Algorithms for Min-k-Overlap Problems Using the Principal Lattice of Partitions Approach. J. Algorithms 21(2): 306-330 (1996) - 1994
- [c2]H. Narayanan, Subir K. Roy, Sachin B. Patkar:
Approximation Algorithms for Min-k-overlap Problems Using the Principal Lattice of Partitions Approach. MFCS 1994: 525-535 - 1993
- [c1]Subir K. Roy, H. Narayanan:
Application of the principal partition and principal lattice of partitions of a graph to the problem of decomposition of a finite state machine. ISCAS 1993: 2564-2567
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