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ORCIDBing-Chen Wu
Person information
- affiliation: Chang-Gung University, Taiwan
- unicode name: 吳秉宸
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2020 – today
- 2023
[j9]Bing-Chen Wu
, Wei-Ting Chen, Tsung-Te Liu:
An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS. IEEE J. Solid State Circuits 58(11): 3275-3285 (2023)- 2022
- [j8]Shih-Hao Cheng, Meng-Hsueh Lee, Bing-Chen Wu, Tsung-Te Liu:
A Lightweight Power Side-Channel Attack Protection Technique With Minimized Overheads Using On-Demand Current Equalizer. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4008-4012 (2022) - 2021
- [c2]Bing-Chen Wu, Tsung-Te Liu:
A Fully Integrated Switched-Capacitor Voltage Regulator with Multi-Rate Successive Approximation Achieving 190 ps Transient FoM and 83.7% Conversion Efficiency. VLSI Circuits 2021: 1-2 - 2020
- [j7]Chen-Hsuan Lu, Ying-Tuan Hsu, Bing-Chen Wu, Tsung-Te Liu:
A 270-mV 6T SRAM Using Row-Based Dual-Phase VDD Control in 28-nm CMOS. IEEE Trans. Circuits Syst. 67-I(12): 4774-4783 (2020)
2010 – 2019
- 2019
- [j6]Shang-Yuan Chang, Bing-Chen Wu, Yi-Long Liou, Rui-Xuan Zheng, Pei-Lin Lee, Tzi-Dar Chiueh, Tsung-Te Liu:
An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3504-3516 (2019) - [j5]Fu-Yan Xie, Bing-Chen Wu, Tsung-Te Liu:
A Ripple Reduction Method for Switched-Capacitor DC-DC Voltage Converter Using Fully Digital Resistance Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3631-3641 (2019) - [c1]Bing-Chen Wu, Tsung-Te Liu:
Variation-Resilient Design Techniques for Energy-Constrained Systems. IOLTS 2019: 228-231 - 2018
- [j4]Bing-Chen Wu, Tsung-Te Liu:
Circuit Sensing Techniques in Magnetoresistive Random-Access Memory. J. Low Power Electron. 14(2): 206-216 (2018) - [j3]Bing-Chen Wu, I-Chyn Wey:
Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 141-153 (2018) - 2015
- [j2]I-Chyn Wey, Bing-Chen Wu, Chien-Chang Peng, Cihun-Siyong Alex Gong, Changhong Yu:
Robust C-element design for soft-error mitigation. IEICE Electron. Express 12(10): 20150268 (2015) - 2014
- [j1]I-Chyn Wey, Yu-Sheng Yang, Bing-Chen Wu, Chien-Chang Peng:
A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design. Microelectron. J. 45(1): 1-13 (2014)
Coauthor Index
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last updated on 2023-11-10 23:57 CET by the dblp team
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