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ORCIDMin Zhu 0001
Person information
- affiliation: Micro Innovation Integrated Circuit Design, Wuxi, China
- affiliation (PhD 2012): Tsinghua University, Institute of Microelectronics, Beijing, China
Other persons with the same name
- Min Zhu — disambiguation page
- Min Zhu 0002
![[0000-0002-5602-2319]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-5602-2319")
— University of Queensland, Business School, QLD, Australia (and 1 more) - Min Zhu 0003 — Xidian University, School of Communications, State Key Laboratory of ISN, Xi'an, China
- Min Zhu 0004 — Zhejiang University, Department of Biomedical Engineering, Hangzhou, China
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2020 – today
- 2024
[j35]Jiangxue Liu, Cankun Zhao, Shuohang Peng, Bohan Yang, Hang Zhao, Xiangdong Han, Min Zhu, Shaojun Wei, Leibo Liu:
A Low-Latency High-Order Arithmetic to Boolean Masking Conversion. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2): 630-653 (2024)- [j34]Xiangren Chen, Bohan Yang, Jianfeng Zhu, Jun Liu, Shuying Yin, Guang Yang, Min Zhu, Shaojun Wei, Leibo Liu:
UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2): 677-713 (2024) - [c10]Yihong Zhu, Wenping Zhu, Yi Ouyang, Junwen Sun, Min Zhu, Qi Zhao, Jinjiang Yang, Chen Chen, Qichao Tao, Guang Yang, Aoyang Zhang, Shaojun Wei, Leibo Liu:
16.2 A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems. ISSCC 2024: 298-300 - [i4]Jiangxue Liu, Cankun Zhao, Shuohang Peng, Bohan Yang, Hang Zhao, Xiangdong Han, Min Zhu, Shaojun Wei, Leibo Liu:
A Low-Latency High-Order Arithmetic to Boolean Masking Conversion. IACR Cryptol. ePrint Arch. 2024: 45 (2024) - 2023
- [j33]Yihong Zhu, Wenping Zhu, Chongyang Li, Min Zhu, Chenchen Deng, Chen Chen, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu:
RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems. IEEE J. Solid State Circuits 58(1): 124-140 (2023) - [j32]Shuqin Su, Bohan Yang, Vladimir Rozic, Mingyuan Yang, Min Zhu, Shaojun Wei, Leibo Liu:
A Closer Look at the Chaotic Ring Oscillators based TRNG Design. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2023(2): 381-417 (2023) - [c9]Yihong Zhu, Wenping Zhu, Chen Chen, Min Zhu, Zhengdong Li, Shaojun Wei, Leibo Liu:
Mckeycutter: A High-throughput Key Generator of Classic McEliece on Hardware. DAC 2023: 1-6 - [i3]Shuqin Su, Bohan Yang, Vladimir Rozic, Mingyuan Yang, Min Zhu, Shaojun Wei, Leibo Liu:
A Closer Look at the Chaotic Ring Oscillators based TRNG Design. IACR Cryptol. ePrint Arch. 2023: 40 (2023) - 2022
- [j31]Yu-Long Zhang, Min Zhu, Donghai Li, Jun-Min Wang:
Stabilization of two coupled wave equations with joint anti-damping and non-collocated control. Autom. 135: 109995 (2022) - [j30]Chenchen Deng, Min Zhu, Jinjiang Yang, Youyu Wu, Jiaji He, Bohan Yang, Jianfeng Zhu, Shouyi Yin, Shaojun Wei, Leibo Liu:
An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance. Sci. China Inf. Sci. 65(4) (2022) - [j29]Zongsheng Hou, Neng Zhang, Bohan Yang, Hanning Wang, Min Zhu, Shouyi Yin, Shaojun Wei, Leibo Liu:
Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2024-2037 (2022) - [j28]Cankun Zhao, Neng Zhang, Hanning Wang, Bohan Yang, Wenping Zhu, Zhengdong Li, Min Zhu, Shouyi Yin, Shaojun Wei, Leibo Liu:
A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1): 270-295 (2022) - [c8]Yihong Zhu, Wenping Zhu, Min Zhu, Chongyang Li, Chenchen Deng, Chen Chen, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu:
A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems. ISSCC 2022: 514-516 - [i2]Yihong Zhu, Wenping Zhu, Chen Chen, Min Zhu, Zhengdong Li, Shaojun Wei, Leibo Liu:
Compact GF(2) systemizer and optimized constant-time hardware sorters for Key Generation in Classic McEliece. IACR Cryptol. ePrint Arch. 2022: 1277 (2022) - 2021
- [j27]Hai Huang, Leibo Liu, Min Zhu, Shouyi Yin, Shaojun Wei:
Fast substitution-box evaluation algorithm and its efficient masking scheme for block ciphers. Sci. China Inf. Sci. 64(8) (2021) - [j26]Yu-Long Zhang, Min Zhu, Donghai Li, Jun-Min Wang:
Static boundary feedback stabilization of an anti-stable wave equation with both collocated and non-collocated measurements. Syst. Control. Lett. 154: 104967 (2021) - [j25]Yihong Zhu, Min Zhu, Bohan Yang, Wenping Zhu, Chenchen Deng, Chen Chen, Shaojun Wei, Leibo Liu:
LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1146-1159 (2021) - 2020
- [j24]Yu-Long Zhang, Min Zhu, Donghai Li, Jun-Min Wang:
Dynamic feedback stabilization of an unstable wave equation. Autom. 121: 109165 (2020) - [j23]Wei Ge, Shenxin Hu, Ji Quan Huang, Bo Liu, Min Zhu:
FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance. IEICE Electron. Express 17(2): 20190670 (2020) - [j22]Wei Ge, Shenghua Chen, Benyu Liu, Min Zhu, Bo Liu:
A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA. IEICE Trans. Inf. Syst. 103-D(5): 1013-1022 (2020) - [j21]Yu-Long Zhang, Min Zhu, Donghai Li, Jun-Min Wang:
ADRC Dynamic Stabilization of an Unstable Heat Equation. IEEE Trans. Autom. Control. 65(10): 4424-4429 (2020) - [j20]Chenchen Deng, Bo Wang, Leibo Liu, Min Zhu, Youyu Wu, Hui Li, Shouyi Yin, Shaojun Wei:
A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 375-379 (2020) - [c7]Ping Wang, Jinjiang Yang, Min Zhu, Bo Liu:
A High-throughput Low-area Entropy Source Based on Asynchronous Feedback Unit. ICCSP 2020: 131-135 - [i1]Yihong Zhu, Min Zhu, Bohan Yang, Wenping Zhu, Chenchen Deng, Chen Chen, Shaojun Wei, Leibo Liu:
A High-performance Hardware Implementation of Saber Based on Karatsuba Algorithm. IACR Cryptol. ePrint Arch. 2020: 1037 (2020)
2010 – 2019
- 2018
- [j19]Leibo Liu, Zhuoquan Zhou, Shaojun Wei, Min Zhu, Shouyi Yin, Shengyang Mao:
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 782-795 (2018) - [j18]Leibo Liu, Bo Wang, Chenchen Deng, Min Zhu, Shouyi Yin, Shaojun Wei:
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3081-3094 (2018) - [c6]Wei Ge, Ji Quan Huang, Bo Liu, Min Zhu, Yuan Cao:
A Deep Learning Modeling Attack Method for MISR-APUF Protection Structures. APCCAS 2018: 398-402 - 2017
- [j17]Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Zhuoquan Zhou, Shaojun Wei:
Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks. IEEE Trans. Inf. Forensics Secur. 12(2): 309-322 (2017) - 2016
- [j16]Leibo Liu, Dong Wang, Yingjie Chen, Min Zhu, Shouyi Yin, Shaojun Wei:
An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform. IEICE Trans. Inf. Syst. 99-D(5): 1285-1295 (2016) - [j15]Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Shaojun Wei:
Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture. IEEE Trans. Inf. Forensics Secur. 11(6): 1151-1164 (2016) - 2015
- [j14]Leibo Liu, Dong Wang, Min Zhu, Yansheng Wang, Shouyi Yin, Peng Cao, Jun Yang, Shaojun Wei:
An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. IEEE Trans. Multim. 17(10): 1706-1720 (2015) - [j13]Leibo Liu, Dong Wang, Min Zhu, Yansheng Wang, Shouyi Yin, Peng Cao, Jun Yang, Shaojun Wei:
Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". IEEE Trans. Multim. 17(12): 2354-2355 (2015) - [c5]Leibo Liu, Yingjie Victor Chen, Dong Wang, Min Zhu, Shouyi Yin, Shaojun Wei:
A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only). FPGA 2015: 267 - 2014
- [j12]Leibo Liu, Yansheng Wang, Shouyi Yin, Min Zhu, Xing Wang, Shaojun Wei:
Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture. Sci. China Inf. Sci. 57(10): 1-18 (2014) - [j11]Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei:
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 983-994 (2014) - [j10]Leibo Liu, Dong Wang, Shouyi Yin, Yingjie Victor Chen, Min Zhu, Shaojun Wei:
SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2635-2648 (2014) - 2013
- [j9]Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei:
Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. Sci. China Inf. Sci. 56(11): 1-20 (2013) - [j8]Hung K. Nguyen, Peng Cao, Xuexiang Wang, Jun Yang, Longxing Shi, Min Zhu, Leibo Liu, Shaojun Wei:
Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip. IEICE Trans. Inf. Syst. 96-D(3): 601-615 (2013) - [j7]Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei:
The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(11): 2218-2229 (2013) - [c4]Leibo Liu, Chenchen Deng, Dong Wang, Min Zhu, Shouyi Yin, Peng Cao, Shaojun Wei:
An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications. CICC 2013: 1-4 - 2012
- [j6]Shouyi Yin, Chongyong Yin, Leibo Liu, Min Zhu, Shaojun Wei:
Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture. IEICE Trans. Inf. Syst. 95-D(2): 335-344 (2012) - [j5]Xinning Liu, Chen Mei, Peng Cao, Min Zhu, Longxing Shi:
Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. IEICE Trans. Inf. Syst. 95-D(2): 374-382 (2012) - [j4]Jian Xiao, Jinguo Zhang, Min Zhu, Jun Yang, Longxing Shi:
Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture. IEICE Trans. Inf. Syst. 95-D(2): 392-402 (2012) - [j3]Bo Liu, Peng Cao, Min Zhu, Jun Yang, Leibo Liu, Shaojun Wei, Longxing Shi:
Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. IEICE Trans. Inf. Syst. 95-D(7): 1858-1871 (2012) - [c3]Shouyi Yin, Chongyong Yin, Leibo Liu, Min Zhu, Yansheng Wang, Shaojun Wei:
Reducing configuration contexts for coarse-grained reconfigurable architecture. ISCAS 2012: 121-124 - 2010
- [j2]Min Zhu, Leibo Liu, Shouyi Yin, Chongyong Yin, Shaojun Wei:
A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System. IEICE Trans. Inf. Syst. 93-D(12): 3202-3210 (2010) - [j1]Tongsheng Geng, Leibo Liu, Shouyi Yin, Min Zhu, Shaojun Wei:
Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System. IEICE Trans. Inf. Syst. 93-D(12): 3223-3231 (2010) - [c2]Tongsheng Geng, Leibo Liu, Shouyi Yin, Min Zhu, Wen Jia, Shaojun Wei:
Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC. ISCAS 2010: 1153-1156 - [c1]Min Zhu, Leibo Liu, Shouyi Yin, Yansheng Wang, Wenjie Wang, Shaojun Wei:
A reconfigurable multi-processor SoC for media applications. ISCAS 2010: 2011-2014
Coauthor Index
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