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Chia-Lin Yang
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Publications
- 2011
- [c38]Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang:
A SAT-based routing algorithm for cross-referencing biochips. SLIP 2011: 1-7 - 2009
- [j13]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang:
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1295-1306 (2009) - [j12]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
T-trees: A tree-based representation for temporal and three-dimensional floorplanning. ACM Trans. Design Autom. Electr. Syst. 14(4): 51:1-51:28 (2009) - 2008
- [j9]Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 643-653 (2008) - [j8]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1928-1941 (2008) - [c30]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang:
A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289 - 2007
- [j6]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. ACM J. Emerg. Technol. Comput. Syst. 3(3): 13 (2007) - [j5]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Temporal floorplanning using the three-dimensional transitive closure subGraph. ACM Trans. Design Autom. Electr. Syst. 12(4): 37 (2007) - [c27]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. ICCAD 2007: 752-757 - [c26]Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen:
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. ICME 2007: 9 - [c25]Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ISLPED 2007: 92-97 - [c24]Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
Efficient obstacle-avoiding rectilinear steiner tree construction. ISPD 2007: 127-134 - 2006
- [c21]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Placement of digital microfluidic biochips using the t-tree formulation. DAC 2006: 931-934 - 2005
- [c16]Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang:
Joint exploration of architectural and physical design spaces with thermal consideration. ISLPED 2005: 123-126 - [c15]Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen:
Reconfigurable Platform for Content Science Research. RTCSA 2005: 481-486 - 2004
- [c14]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen:
Temporal floorplanning using 3D-subTCG. ASP-DAC 2004: 725-730 - [c10]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Temporal floorplanning using the T-tree formulation. ICCAD 2004: 300-305
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