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Kris Gaj

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Chang Shu 0003

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Publications

2009
[j8]
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  - https://dblp.org/rec/journals/tc/ShuKG09
Chang Shu, Soonhak Kwon, Kris Gaj:
Reconfigurable Computing Approach for Tate Pairing Cryptosystems over Binary Fields. IEEE Trans. Computers 58(9): 1221-1237 (2009)
2008
[j6]
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  - journals/iet-cdt/ShuKG08
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Chang Shu, Soonhak Kwon, Kris Gaj:
FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials. IET Comput. Digit. Tech. 2(1): 6-11 (2008)
[j5]
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  - journals/pc/SahaEHTLESGMB08
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Proshanta Saha, Esam El-Araby, Miaoqing Huang, Mohamed Taher, Sergio López-Buedo, Tarek A. El-Ghazawi, Chang Shu, Kris Gaj, Alan Michalski, Duncan A. Buell:
Portable library development for reconfigurable computing systems: A case study. Parallel Comput. 34(4-5): 245-260 (2008)
2006
[c35]
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  - conf/fpt/ShuKG06
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Chang Shu, Soonhak Kwon, Kris Gaj:
FPGA accelerated tate pairing based cryptosystems over binary fields. FPT 2006: 173-180
[i1]
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  - electronic edition @ iacr.org (open access)
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  - journals/iacr/ShuKG06
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Chang Shu, Soonhak Kwon, Kris Gaj:
FPGA Accelerated Tate Pairing Based Cryptosystems over Binary Fields. IACR Cryptol. ePrint Arch. 2006: 179 (2006)
2005
[c29]
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  - conf/fpt/ShuGE05
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Chang Shu, Kris Gaj, Tarek A. El-Ghazawi:
Low Latency Elliptic Curve Cryptography Accelerators for NIST Curves Over Binary Fields. FPT 2005: 309-310
2004
[c20]
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  - conf/fpga/BajracharyaSGE04
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Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi:
Implementation of elliptic curve cryptosystems over GF(2ⁿ) in optimal normal basis on a reconfigurable computer. FPGA 2004: 259
[c19]
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  - conf/fpl/BajracharyaSGE04
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Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi:
Implementation of Elliptic Curve Cryptosystems over GF(2ⁿ) in Optimal Normal Basis on a Reconfigurable Computer. FPL 2004: 1001-1005

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