Matthew K. Farrens

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Andrew R. Pleszkun

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Publications

1997
[j6]
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Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun:
Managing data caches using selective cache line replacement. Int. J. Parallel Program. 25(3): 213-242 (1997)
1995
[c16]
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Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun:
A modified approach to data cache management. MICRO 1995: 93-103
1994
[c15]
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Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun:
A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. ISCA 1994: 338-347
1992
[c10]
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Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun:
MISC: a Multiple Instruction Stream Computer. MICRO 1992: 193-196
1991
[j1]
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Matthew K. Farrens, Andrew R. Pleszkun:
Implementation of the PIPE Processor. Computer 24(1): 65-69 (1991)
[c7]
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Matthew K. Farrens, Andrew R. Pleszkun:
Strategies for Achieving Improved Processor Throughput. ISCA 1991: 362-369
1990
[c2]
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  - electronic edition @ acm.org
  - no references & citations available
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Matthew K. Farrens, Andrew R. Pleszkun:
An evaluation of functional unit lengths for single-chip processors. MICRO 1990: 209-215
1989
[c1]
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Matthew K. Farrens, Andrew R. Pleszkun:
Improving Performance of Small On-Chip Instruction Caches. ISCA 1989: 234-241

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