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Federico Angiolini
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Publications
- 2008
- [j7]David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli:
Network-on-Chip design and synthesis outlook. Integr. 41(3): 340-359 (2008) - 2007
- [j5]Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini:
Bringing NoCs to 65 nm. IEEE Micro 27(5): 75-85 (2007) - [c20]Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli:
Interactive presentation: Improving the fault tolerance of nanometric PLA designs. DATE 2007: 570-575 - [c18]Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini:
NoC Design and Implementation in 65nm Technology. NOCS 2007: 273-282 - 2006
- [c15]Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo:
Designing application-specific networks on chips with floorplan information. ICCAD 2006: 355-362 - [c14]Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
Reliability Support for On-Chip Memories Using Networks-on-Chip. ICCD 2006: 389-396 - [c13]Srinivasan Murali, Rutuparna Tamhankar, Federico Angiolini, Antonio Pullini, David Atienza, Luca Benini, Giovanni De Micheli:
Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips. SoC 2006: 1-4 - [c11]Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo:
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. VLSI-SoC 2006: 158-163 - [c10]Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo:
Designing Routing and Message-Dependent Deadlock Free Networks on Chips. VLSI-SoC (Selected Papers) 2006: 337-355
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