Sai Phaneendra P.

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with M. B. Srinivas

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Publications

2022
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P. Sai Phaneendra, Chetan Vudadha, M. B. Srinivas:
Optimization of Reversible Circuits Using Gate Pair Classification. SN Comput. Sci. 3(1): 40 (2022)
2018
[j1]
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Chetan Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas:
Energy efficient design of CNFET-based multi-digit ternary adders. Microelectron. J. 75: 75-86 (2018)
2017
[c13]
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Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas:
Optimizing the Reversible Circuits Using Complementary Control Line Transformation. RC 2017: 111-126
[c12]
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Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas:
An ESOP Based Cube Decomposition Technique for Reversible Circuits. RC 2017: 127-140
2016
[c11]
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Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas:
An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. iNIS 2016: 278-283
2014
[c10]
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Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika:
A New Design of an N-Bit Reversible Arithmetic Logic Unit. ISED 2014: 224-225
[c9]
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P. Sai Phaneendra, Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas:
An Optimized Design of Reversible Quantum Comparator. VLSID 2014: 557-562
2012
[c8]
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Chetan Vudadha, Phaneendra P. Sai, Sreehari Veeramachaneni, M. B. Srinivas:
CNFET based ternary magnitude comparator. ISCIT 2012: 942-946
[c7]
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Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas:
Design of Prefix-Based Optimal Reversible Comparator. ISVLSI 2012: 201-206
[c6]
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Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas:
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. ISVLSI 2012: 225-230
[c5]
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Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design 2012: 280-285
2011
[c4]
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Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Unified Architecture for BCD and Binary Adder/Subtractor. DSD 2011: 426-429
[c3]
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P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. ISCIT 2011: 472-477
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Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. ISED 2011: 100-105
[c1]
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Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Prefix Based Reconfigurable Adder. ISVLSI 2011: 349-350

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