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Georg Sigl

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Philipp Koppermann

> Home > Persons > Georg Sigl

Publications

2018
[j14]
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  - journals/tches/KoppermannSHS18
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  - https://dblp.org/rec/journals/tches/KoppermannSHS18
Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl:
Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018(1): 1-17 (2018)
[c81]
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  - conf/fdtc/SelmkeZKMHS18
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  - https://dblp.org/rec/conf/fdtc/SelmkeZKMHS18
Bodo Selmke, Kilian Zinnecker, Philipp Koppermann, Katja Miller, Johann Heyszl, Georg Sigl:
Locked out by Latch-up? An Empirical Study on Laser Fault Injection into Arm Cortex-M Processors. FDTC 2018: 7-14
[i9]
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  - electronic edition @ iacr.org (open access)
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  - journals/iacr/KoppermannPHS18
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Philipp Koppermann, Eduard Pop, Johann Heyszl, Georg Sigl:
18 Seconds to Key Exchange: Limitations of Supersingular Isogeny Diffie-Hellman on Embedded Devices. IACR Cryptol. ePrint Arch. 2018: 932 (2018)
2017
[j10]
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  - journals/mam/KoppermannSHS17
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Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl:
Low-latency X25519 hardware implementation: breaking the 100 microseconds barrier. Microprocess. Microsystems 52: 491-497 (2017)
[c68]
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  - conf/host/KoppermannSHS17
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Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl:
Automatic generation of high-performance modular multipliers for arbitrary mersenne primes on FPGAs. HOST 2017: 35-40
[i7]
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Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl:
Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve. IACR Cryptol. ePrint Arch. 2017: 814 (2017)
2016
[c53]
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  - conf/dsd/KoppermannSHS16
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  - https://dblp.org/rec/conf/dsd/KoppermannSHS16
Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl:
X25519 Hardware Implementation for Low-Latency Applications. DSD 2016: 99-106

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