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Henrik Eriksson

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Per Larsson-Edefors

> Home > Persons > Henrik Eriksson

Publications

2009
[c41]
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  - conf/icecsys/KimforsBHSSEL09
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Patrik Kimfors, Niklas Broman, Andreas Haraldsson, Kasyab P. Subramaniyan, Magnus Själander, Henrik Eriksson, Per Larsson-Edefors:
Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree. ICECS 2009: 77-80
2006
[j25]
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  - journals/tvlsi/ErikssonLE06
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Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert:
Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 370-379 (2006)
[c34]
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  - conf/iscas/ErikssonLSSJS06
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Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, Daniel Johansson, Martin Scholin:
Multiplier reduction tree with logarithmic logic depth and regular connectivity. ISCAS 2006
2005
[c30]
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  - conf/iscas/SjalanderDLE05
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  - https://dblp.org/rec/conf/iscas/SjalanderDLE05
Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson:
A low-leakage twin-precision multiplier using reconfigurable power gating. ISCAS (2) 2005: 1654-1657
2004
[c29]
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  - conf/esscirc/DraidiiulisLEE04
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Mindaugas Draidiiulis, Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson:
A power cut-off technique for gate leakage suppression [CMOS logic circuits]. ESSCIRC 2004: 171-174
[c28]
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  - conf/iccd/SjalanderEL04
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Magnus Själander, Henrik Eriksson, Per Larsson-Edefors:
An Efficient Twin-Precision Multiplier. ICCD 2004: 30-33
[c27]
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Henrik Eriksson, Per Larsson-Edefors:
Glitch-conscious low-power design of arithmetic circuits. ISCAS (2) 2004: 281-284
[c26]
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  - conf/iscas/ErikssonL04a
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Henrik Eriksson, Per Larsson-Edefors:
Dynamic pass-transistor dot operators for efficient parallel-prefix adders. ISCAS (2) 2004: 461-464
2003
[c19]
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  - conf/aspdac/ErikssonLHS03
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Henrik Eriksson, Per Larsson-Edefors, Tomas Henriksson, Christer Svensson:
Full-custom vs. standard-cell design flow: an adder case study. ASP-DAC 2003: 507-510
[c18]
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  - conf/isvlsi/Larsson-EdeforsEES03
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Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson:
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. ISVLSI 2003: 225-230
2001
[c15]
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  - conf/icecsys/HenrikssonENLL01
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Tomas Henriksson, Henrik Eriksson, Ulf Nordqvist, Per Larsson-Edefors, Dake Liu:
VLSI implementation of CRC-32 for 10 Gigabit Ethernet. ICECS 2001: 1215-1218
[c14]
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  - conf/iscas/ErikssonLA01
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Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour:
A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. ISCAS (4) 2001: 84-87
[c13]
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  - conf/iscas/ErikssonLM01
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Henrik Eriksson, Per Larsson-Edefors, William P. Marnane:
A regular parallel multiplier which utilizes multiple carry-propagate adders. ISCAS (4) 2001: 166-169
2000
[c10]
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  - conf/iscas/EckerbertELE00
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Daniel Eckerbert, Henrik Eriksson, Per Larsson-Edefors, Anders Edman:
An interconnect-driven design of a DFT processor. ISCAS 2000: 569-572
[c9]
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  - conf/patmos/ErikssonL00
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Henrik Eriksson, Per Larsson-Edefors:
Impact of Voltage Scaling on Glitch Power Consumption. PATMOS 2000: 139-148

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