Federico Angiolini

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Antonio Pullini

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Publications

2011
[j10]
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  - journals/jssc/PlasLLMOTTLSKVCVSWLPBMCROPBORWDNAPABDTBM11
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Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal:
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46(1): 293-307 (2011)
2010
[c26]
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  - conf/dac/MicheliSMBAP10
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Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini:
Networks on Chips: from research to products. DAC 2010: 300-305
2009
[c22]
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  - conf/socc/KakoeeAMPSB09
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Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini:
A floorplan-aware interactive tool flow for NoC design and synthesis. SoCC 2009: 379-382
2008
[j7]
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  - journals/integration/AtienzaAMPBM08
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David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli:
Network-on-Chip design and synthesis outlook. Integr. 41(3): 340-359 (2008)
2007
[j5]
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  - journals/micro/PulliniAMAMB07
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Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini:
Bringing NoCs to 65 nm. IEEE Micro 27(5): 75-85 (2007)
[j3]
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  - journals/tcad/TamhankarMSPABM07
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Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli:
Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1297-1310 (2007)
[c18]
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  - conf/nocs/PulliniAMAMRMB07
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Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini:
NoC Design and Implementation in 65nm Technology. NOCS 2007: 273-282
2006
[c13]
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  - conf/issoc/MuraliTAPABM06
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Srinivasan Murali, Rutuparna Tamhankar, Federico Angiolini, Antonio Pullini, David Atienza, Luca Benini, Giovanni De Micheli:
Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips. SoC 2006: 1-4
2005
[c6]
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  - conf/sbcci/PulliniABB05
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Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini:
Fault tolerance overhead in network-on-chip flow control schemes. SBCCI 2005: 224-229

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