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ORCIDJoel S. Emer
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- award (2009): Eckert-Mauchly Award
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Books and Theses
- 2020
[b2]Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer:
Efficient Processing of Deep Neural Networks. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2020, ISBN 978-3-031-00638-8- 1979
- [b1]Joel S. Emer:
Shared Resources for Multiple Instruction Stream Pipelined Processors. University of Illinois Urbana-Champaign, USA, 1979
Journal Articles
- 2023
- [j28]Michael Pellauer
, Jason Clemons, Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Donghyuk Lee, Mike O'Connor, Anghsuman Parashar, Sean Treichler, Po-An Tsai, Stephen W. Keckler, Joel S. Emer:
Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing. ACM Trans. Comput. Syst. 41: 4:1-4:30 (2023) - 2021
- [j27]Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler:
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64(6): 107-116 (2021) - 2020
- [j26]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany:
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55(4): 920-932 (2020) - 2019
- [j25]Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer, Vivienne Sze:
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 292-308 (2019) - 2017
- [j24]Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze:
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks. IEEE J. Solid State Circuits 52(1): 127-138 (2017) - [j23]Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators. IEEE Micro 37(3): 12-21 (2017) - [j22]Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer:
Efficient Processing of Deep Neural Networks: A Tutorial and Survey. Proc. IEEE 105(12): 2295-2329 (2017) - [j21]Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Michael Adler, Joel S. Emer:
(FPL 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies. ACM Trans. Reconfigurable Technol. Syst. 10(2): 13:1-13:23 (2017) - 2016
- [j20]Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Sánchez:
Unlocking Ordered Parallelism with the Swarm Architecture. IEEE Micro 36(3): 105-117 (2016) - 2015
- [j19]Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer:
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33(3): 10:1-10:32 (2015) - 2014
- [j18]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34(3): 120-137 (2014) - 2013
- [j17]Samantika Subramaniam, Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl J. Beckmann, Tryggve Fossum, Joel S. Emer:
Using in-flight chains to build a scalable cache coherence protocol. ACM Trans. Archit. Code Optim. 10(4): 28:1-28:24 (2013) - 2012
- [j16]William Hasenplaugh, Pritpal S. Ahuja, Aamer Jaleel, Simon C. Steely Jr., Joel S. Emer:
The gradient-based cache partitioning algorithm. ACM Trans. Archit. Code Optim. 8(4): 44:1-44:21 (2012) - 2010
- [j15]James C. Hoe, Doug Burger, Joel S. Emer, Derek Chiou, Resit Sendag, Joshua J. Yi:
The Future of Architectural Simulation. IEEE Micro 30(3): 8-18 (2010) - 2009
- [j14]Joel S. Emer, Dean M. Tullsen:
Guest Editors' Introduction: Top Picks from the 2008 Computer Architecture Conferences. IEEE Micro 29(1): 6-9 (2009) - [j13]Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(3): 16:1-16:26 (2009) - 2008
- [j12]Arijit Biswas, Paul Racunas, Joel S. Emer, Shubhendu S. Mukherjee:
Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal. IEEE Comput. Archit. Lett. 7(1): 21-24 (2008) - [j11]Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer:
Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro 28(1): 91-98 (2008) - 2007
- [j10]Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag:
Single-Threaded vs. Multithreaded: Where Should We Focus? IEEE Micro 27(6): 14-24 (2007) - 2004
- [j9]Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt:
Reducing the Soft-Error Rate of a High-Performance Microprocessor. IEEE Micro 24(6): 30-37 (2004) - 2003
- [j8]Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin:
Measuring Architectural Vulnerability Factors. IEEE Micro 23(6): 70-75 (2003) - 2002
- [j7]Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson:
Performance Simulation Tools. Computer 35(2): 38-39 (2002) - [j6]Joel S. Emer, Pritpal S. Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan:
Asim: A Performance Model Framework. Computer 35(2): 68-76 (2002) - 1997
- [j5]Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm, Dean M. Tullsen:
Simultaneous multithreading: a platform for next-generation processors. IEEE Micro 17(5): 12-19 (1997) - [j4]Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen:
Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. ACM Trans. Comput. Syst. 15(3): 322-354 (1997) - 1996
- [j3]Joel S. Emer:
Incremental Versus Revolutionary Research. ACM Comput. Surv. 28(4es): 27 (1996) - 1989
- [j2]K. K. Ramakrishnan, Joel S. Emer:
Performance Analysis of Mass Storage Service Alternatives for Distributed Systems. IEEE Trans. Software Eng. 15(2): 120-133 (1989) - 1985
- [j1]Douglas W. Clark, Joel S. Emer:
Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement. ACM Trans. Comput. Syst. 3(1): 31-62 (1985)
Conference and Workshop Papers
- 2023
- [c101]Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher:
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling. ASPLOS (3) 2023: 18-32 - [c100]Olivia Hsu, Maxwell Strange, Ritvik Sharma, Jaeyeon Won, Kunle Olukotun, Joel S. Emer, Mark A. Horowitz, Fredrik Kjølstad:
The Sparse Abstract Machine. ASPLOS (3) 2023: 710-726 - [c99]Jaeyeon Won, Charith Mendis, Joel S. Emer, Saman P. Amarasinghe:
WACO: Learning Workload-Aware Co-optimization of the Format and Schedule of a Sparse Tensor Program. ASPLOS (2) 2023: 920-934 - [c98]Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer:
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. DCC 2023: 373 - [c97]Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher:
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract). HOPC@SPAA 2023: 15-16 - [c96]Yifan Yang, Joel S. Emer, Daniel Sánchez:
ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining. HPCA 2023: 598-610 - [c95]Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer:
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. HPEC 2023: 1-7 - [c94]Tanner Andrulis, Joel S. Emer, Vivienne Sze:
RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required! ISCA 2023: 27:1-27:16 - [c93]Peter W. Deutsch, Weon Taek Na, Thomas Bourgeat, Joel S. Emer, Mengjia Yan:
Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes. ISCA 2023: 38:1-38:16 - [c92]Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators. ISPASS 2023: 316-318 - [c91]Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, Joel S. Emer, Daniel Sánchez:
Accelerating RTL Simulation with Hardware-Software Co-Design. MICRO 2023: 153-166 - [c90]Kyungmi Lee, Mengjia Yan, Joel S. Emer, Anantha P. Chandrakasan:
SecureLoop: Design Space Exploration of Secure DNN Accelerators. MICRO 2023: 194-208 - [c89]Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. MICRO 2023: 1106-1120 - [c88]Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer:
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. MICRO 2023: 1255-1270 - [c87]Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze:
Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. MICRO 2023: 1347-1363 - 2022
- [c86]Peter W. Deutsch, Yuheng Yang, Thomas Bourgeat, Jules Drean, Joel S. Emer, Mengjia Yan:
DAGguise: mitigating memory timing side channels. ASPLOS 2022: 329-343 - [c85]Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel S. Emer, Siddharth Joshi:
Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization. ISPASS 2022: 254-266 - [c84]Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. MICRO 2022: 1377-1395 - 2021
- [c83]Guowei Zhang, Nithya Attaluri, Joel S. Emer, Daniel Sánchez:
Gamma: leveraging Gustavson's algorithm to accelerate sparse matrix multiplication. ASPLOS 2021: 687-701 - [c82]Yifan Yang, Joel S. Emer, Daniel Sánchez:
SpZip: Architectural Support for Effective Data Compression In Irregular Applications. ISCA 2021: 1069-1082 - [c81]Francis Wang, Yannan Nellie Wu, Matthew E. Woicik, Joel S. Emer, Vivienne Sze:
Architecture-Level Energy Estimation for Heterogeneous Computing Systems. ISPASS 2021: 229-231 - [c80]Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. ISPASS 2021: 232-234 - [c79]Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, Abdulrahman Mahmoud, Saugata Ghose, Joel S. Emer:
Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future. WCAE 2021: 1-9 - 2020
- [c78]Yannan Nellie Wu, Vivienne Sze, Joel S. Emer:
An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs. ISPASS 2020: 116-118 - [c77]Thomas Bourgeat, Jules Drean, Yuheng Yang, Lillian Tsai, Joel S. Emer, Mengjia Yan:
CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches. MICRO 2020: 1110-1123 - 2019
- [c76]Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer:
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. ASPLOS 2019: 137-151 - [c75]Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany:
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium 2019: 1-24 - [c74]Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany:
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD 2019: 1-8 - [c73]Yannan Nellie Wu, Joel S. Emer, Vivienne Sze:
Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs. ICCAD 2019: 1-8 - [c72]Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer:
Timeloop: A Systematic Approach to DNN Accelerator Evaluation. ISPASS 2019: 304-315 - [c71]Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler:
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO 2019: 14-27 - [c70]Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher:
ExTensor: An Accelerator for Sparse Tensor Algebra. MICRO 2019: 319-333 - [c69]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany:
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits 2019: 300- - 2018
- [c68]Vivienne Sze, Yu-Hsin Chen, Joel S. Emer, Amr Suleiman, Zhengdong Zhang:
Hardware for machine learning: Challenges and opportunities. CICC 2018: 1-8 - [c67]Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer:
A modular digital VLSI flow for high-productivity SoC design. DAC 2018: 72:1-72:6 - [c66]Mark C. Jeffrey, Victor A. Ying, Suvinay Subramanian, Hyun Ryong Lee, Joel S. Emer, Daniel Sánchez:
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism. MICRO 2018: 217-230 - [c65]Vladimir Kiriansky, Ilia A. Lebedev, Saman P. Amarasinghe, Srinivas Devadas, Joel S. Emer:
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors. MICRO 2018: 974-987 - 2017
- [c64]Maleen Abeydeera, Suvinay Subramanian, Mark C. Jeffrey, Joel S. Emer, Daniel Sánchez:
SAM: Optimizing Multithreaded Cores for Speculative Parallelism. PACT 2017: 64-78 - [c63]Tien-Ju Yang, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
A method to estimate the energy consumption of deep neural networks. ACSSC 2017: 1916-1920 - [c62]Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer:
Automatic Construction of Program-Optimized FPGA Memory Networks. FPGA 2017: 125-134 - [c61]Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally:
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. ISCA 2017: 27-40 - [c60]Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel S. Emer, Daniel Sánchez:
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism. ISCA 2017: 587-599 - [c59]Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Towards closing the energy gap between HOG and CNN features for embedded vision (Invited paper). ISCAS 2017: 1-4 - [c58]Siva Kumar Sastry Hari, Timothy Tsai, Mark Stephenson, Stephen W. Keckler, Joel S. Emer:
SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation. ISPASS 2017: 249-258 - [c57]Guanpeng Li, Siva Kumar Sastry Hari, Michael B. Sullivan, Timothy Tsai, Karthik Pattabiraman, Joel S. Emer, Stephen W. Keckler:
Understanding error propagation in deep learning neural network (DNN) accelerators and applications. SC 2017: 8 - 2016
- [c56]Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer:
LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning. FPGA 2016: 128-137 - [c55]Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks. ISCA 2016: 367-379 - [c54]Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze:
14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. ISSCC 2016: 262-263 - [c53]Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel S. Emer, Stephen W. Keckler:
CLARA: Circular Linked-List Auto and Self Refresh Architecture. MEMSYS 2016: 338-349 - [c52]Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel S. Emer, Daniel Sánchez:
Data-centric execution of speculative parallel programs. MICRO 2016: 5:1-5:13 - 2015
- [c51]Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer:
Scavenger: Automating the construction of application-optimized memory hierarchies. FPL 2015: 1-8 - [c50]Aamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C. Steely Jr., Joel S. Emer:
High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches. HPCA 2015: 343-353 - [c49]Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Sánchez:
A scalable architecture for ordered parallelism. MICRO 2015: 228-241 - [c48]Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer:
A fast and accurate analytical technique to compute the AVF of sequential bits in a processor. MICRO 2015: 738-749 - 2014
- [c47]Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer:
LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories. FCCM 2014: 117-124 - [c46]Kermin Fleming, Hsin-Jung Yang, Michael Adler, Joel S. Emer:
The LEAP FPGA operating system. FPL 2014: 1-8 - [c45]Jesmin Jahan Tithi, Neal Clayton Crago, Joel S. Emer:
Exploiting spatial architectures for edit distance algorithms. ISPASS 2014: 23-34 - 2013
- [c44]Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer:
Optimizing under abstraction: Using prefetching to improve FPGA performance. FPL 2013: 1-8 - [c43]Peng Li, Angshuman Parashar, Michael Pellauer, Tao Wang, Joel S. Emer:
A Hierarchical Architectural Framework for Reconfigurable Logic Computing. IPDPS Workshops 2013: 287-292 - [c42]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA 2013: 142-153 - 2012
- [c41]Aamer Jaleel, Hashem Hashemi Najaf-abadi, Samantika Subramaniam, Simon C. Steely Jr., Joel S. Emer:
CRUISE: cache replacement and utility-aware scheduling. ASPLOS 2012: 249-260 - [c40]Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer:
Leveraging latency-insensitivity to ease multiple FPGA design. FPGA 2012: 175-184 - [c39]Sang Woo Jun, Kermin Fleming, Michael Adler, Joel S. Emer:
ZIP-IO: Architecture for application-specific compression of Big Data. FPT 2012: 343-351 - [c38]Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer:
Scheduling heterogeneous multi-cores through performance impact estimation (PIE). ISCA 2012: 213-224 - 2011
- [c37]Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer:
Leap scratchpads: automatic memory and cache management for reconfigurable logic. FPGA 2011: 25-28 - [c36]Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer:
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. HPCA 2011: 406-417 - [c35]Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer:
SHiP: signature-based hit predictor for high performance caching. MICRO 2011: 430-441 - [c34]Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer:
PACMan: prefetch-aware cache management for high performance caching. MICRO 2011: 442-453 - 2010
- [c33]Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer:
High performance cache replacement using re-reference interval prediction (RRIP). ISCA 2010: 60-71 - [c32]Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer:
Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). MEMOCODE 2010: 69-72 - [c31]Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer:
Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies. MICRO 2010: 151-162 - 2009
- [c30]Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer:
Soft connections: addressing the hardware-design modularity problem. DAC 2009: 276-281 - [c29]Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi:
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. HPCA 2009: 289-300 - [c28]Joel S. Emer:
Accelerating architecture research. ISPASS 2009 - 2008
- [c27]Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer:
Adaptive insertion policies for managing shared caches. PACT 2008: 208-219 - [c26]Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA 2008: 87-96 - [c25]Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS 2008: 1-10 - 2007
- [c24]Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler:
Late-binding: enabling unordered load-store queues. ISCA 2007: 347-357 - [c23]Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer:
Adaptive insertion policies for high performance caching. ISCA 2007: 381-391 - 2005
- [c22]Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt:
The Soft Error Problem: An Architectural Perspective. HPCA 2005: 243-247 - [c21]Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan:
Computing Architectural Vulnerability Factors for Address-Based Structures. ISCA 2005: 532-543 - 2004
- [c20]Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt:
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. ISCA 2004: 264-275 - [c19]Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt:
Cache Scrubbing in Microprocessors: Myth or Necessity? PRDC 2004: 37-42 - 2003
- [c18]Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin:
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. MICRO 2003: 29-42 - 2002
- [c17]Shubhendu S. Mukherjee, Federico Silla, Peter J. Bannon, Joel S. Emer, Steven Lang, David Webb:
A comparative study of arbitration algorithms for the Alpha 21364 pipelined router. ASPLOS 2002: 223-234 - [c16]Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer:
Loose Loops Sink Chips. HPCA 2002: 299-310 - [c15]Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec:
Tarantula: A Vector Extension to the Alpha Architecture. ISCA 2002: 281-292 - 2000
- [c14]Harish Patil, Joel S. Emer:
Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing. HPCA 2000: 251-262 - 1999
- [c13]Timothy Sherwood, Brad Calder, Joel S. Emer:
Reducing cache misses using hardware and software page placement. International Conference on Supercomputing 1999: 155-164 - [c12]Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi:
The Use of Multithreading for Exception Handling. MICRO 1999: 219-229 - 1998
- [c11]Joel S. Emer, Douglas W. Clark:
Retrospective: Characterization of Processor Performance in the VAX-11/780. 25 Years ISCA: Retrospectives and Reprints 1998: 37-38 - [c10]George Z. Chrysos, Joel S. Emer:
Memory Dependence Prediction Using Store Sets. ISCA 1998: 142-153 - [c9]Joel S. Emer, Douglas W. Clark:
A Characterization of Processor Performance in the VAX-11/780. 25 Years ISCA: Retrospectives and Reprints 1998: 274-283 - 1997
- [c8]Joel S. Emer, Nicholas C. Gloy:
A Language for Describing Predictors and Its Application to Automatic Synthesis. ISCA 1997: 304-314 - 1996
- [c7]Brad Calder, Dirk Grunwald, Joel S. Emer:
Predictive Sequential Associative Cache. HPCA 1996: 244-253 - [c6]Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm:
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. ISCA 1996: 191-202 - 1995
- [c5]Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer:
Instruction Fetching: Coping with Code Bloat. ISCA 1995: 345-356 - [c4]Brad Calder, Dirk Grunwald, Joel S. Emer:
A system level perspective on branch architecture performance. MICRO 1995: 199-206 - 1988
- [c3]Joel S. Emer, K. K. Ramakrishnan:
Performance Considerations for Distributed Services: A Case Study: Mass Storage. ICDCS 1988: 289-297 - 1986
- [c2]Joel S. Emer, K. K. Ramakrishnan:
Design analysis of a heterogeneous distributed system. ACM SIGOPS European Workshop 1986 - 1984
- [c1]Joel S. Emer, Douglas W. Clark:
A Characterization of Processor Performance in the VAX-11/780. ISCA 1984: 301-310
Editorship
- 2017
- [e4]Hillery C. Hunter, Jaime Moreno, Joel S. Emer, Daniel Sánchez:
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017. ACM 2017, ISBN 978-1-4503-4952-9 [contents] - 2009
- [e3]André Seznec, Joel S. Emer, Michael F. P. O'Boyle, Margaret Martonosi, Theo Ungerer:
High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings. Lecture Notes in Computer Science 5409, Springer 2009, ISBN 978-3-540-92989-5 [contents] - 2000
- [e2]Alan D. Berenbaum, Joel S. Emer:
27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada. IEEE Computer Society 2000, ISBN 978-1-58113-232-8 [contents] - 1989
- [e1]Joel S. Emer, John L. Hennessy:
ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989. ACM Press 1989, ISBN 0-89791-300-0 [contents]
Reference Works
- 2011
- [r1]Joel S. Emer, Tryggve Fossum:
DEC Alpha. Encyclopedia of Parallel Computing 2011: 535-545
Informal and Other Publications
- 2023
- [i15]Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer:
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. CoRR abs/2304.07931 (2023) - [i14]Tanner Andrulis, Joel S. Emer, Vivienne Sze:
RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required! CoRR abs/2304.07935 (2023) - [i13]Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. CoRR abs/2305.12718 (2023) - [i12]Weon Taek Na, Joel S. Emer, Mengjia Yan:
Penetrating Shields: A Systematic Analysis of Memory Corruption Mitigations in the Spectre Era. CoRR abs/2309.04119 (2023) - [i11]Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze:
Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. CoRR abs/2310.00192 (2023) - 2022
- [i10]Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. CoRR abs/2205.05826 (2022) - [i9]Olivia Hsu, Maxwell Strange, Jaeyeon Won, Ritvik Sharma, Kunle Olukotun, Joel S. Emer, Mark Horowitz, Fredrik Kjolstad:
The Sparse Abstract Machine. CoRR abs/2208.14610 (2022) - 2020
- [i8]Siva Kumar Sastry Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip P. Shirvani, Paul Racunas, Joel S. Emer, Stephen W. Keckler:
Estimating Silent Data Corruption Rates Using a Two-Level Model. CoRR abs/2005.01445 (2020) - [i7]Liane Bernstein, Alexander Sludds, Ryan Hamerly, Vivienne Sze, Joel S. Emer, Dirk R. Englund:
Freely scalable and reconfigurable optical hardware for deep learning. CoRR abs/2006.13926 (2020) - 2018
- [i6]Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Eyeriss v2: A Flexible and High-Performance Accelerator for Emerging Deep Neural Networks. CoRR abs/1807.07928 (2018) - [i5]Vladimir Kiriansky, Ilia A. Lebedev, Saman P. Amarasinghe, Srinivas Devadas, Joel S. Emer:
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors. IACR Cryptol. ePrint Arch. 2018: 418 (2018) - 2017
- [i4]Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Towards Closing the Energy Gap Between HOG and CNN Features for Embedded Vision. CoRR abs/1703.05853 (2017) - [i3]Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer:
Efficient Processing of Deep Neural Networks: A Tutorial and Survey. CoRR abs/1703.09039 (2017) - [i2]Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally:
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. CoRR abs/1708.04485 (2017) - 2016
- [i1]Vivienne Sze, Yu-Hsin Chen, Joel S. Emer, Amr Suleiman, Zhengdong Zhang:
Hardware for Machine Learning: Challenges and Opportunities. CoRR abs/1612.07625 (2016)
Coauthor Index
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