BibTeX record conf/IEEEpact/HuangN14

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@inproceedings{DBLP:conf/IEEEpact/HuangN14,
  author       = {Cheng{-}Chieh Huang and
                  Vijay Nagarajan},
  editor       = {Jos{\'{e}} Nelson Amaral and
                  Josep Torrellas},
  title        = {ATCache: reducing {DRAM} cache latency via a small {SRAM} tag cache},
  booktitle    = {International Conference on Parallel Architectures and Compilation,
                  {PACT} '14, Edmonton, AB, Canada, August 24-27, 2014},
  pages        = {51--60},
  publisher    = {{ACM}},
  year         = {2014},
  url          = {https://doi.org/10.1145/2628071.2628089},
  doi          = {10.1145/2628071.2628089},
  timestamp    = {Tue, 06 Nov 2018 11:07:48 +0100},
  biburl       = {https://dblp.org/rec/conf/IEEEpact/HuangN14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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