BibTeX record conf/cicc/SinghKPVNB11

• > Home > conf/cicc/SinghKPVNB11

@inproceedings{DBLP:conf/cicc/SinghKPVNB11,
  author       = {Vikas Singh and
                  Nagendra Krishnapura and
                  Shanthi Pavan and
                  Baradwaj Vigraham and
                  Nimit Nigania and
                  Debasish Behera},
  editor       = {Rakesh Patel and
                  Tom Andre and
                  Aurangzeb Khan},
  title        = {A 16MHz {BW} 75dB {DR} {CT} {\(\Delta\)}{\(\Sigma\)} {ADC} compensated
                  for more than one cycle excess loop delay},
  booktitle    = {2011 {IEEE} Custom Integrated Circuits Conference, {CICC} 2011, San
                  Jose, CA, USA, Sept. 19-21, 2011},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/CICC.2011.6055291},
  doi          = {10.1109/CICC.2011.6055291},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/SinghKPVNB11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}