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BibTeX record conf/vlsi-dat/LinTYLWCJHLLS12
@inproceedings{DBLP:conf/vlsi-dat/LinTYLWCJHLLS12, author = {Yi{-}Wei Lin and Ming{-}Chien Tsai and Hao{-}I Yang and Geng{-}Cing Lin and Shao{-}Cheng Wang and Ching{-}Te Chuang and Shyh{-}Jye Jou and Wei Hwang and Nan{-}Chun Lien and Kuen{-}Di Lee and Wei{-}Chiang Shih}, title = {An all-digital Read Stability and Write Margin characterization scheme for {CMOS} 6T {SRAM} array}, booktitle = {Proceedings of Technical Program of 2012 {VLSI} Design, Automation and Test, {VLSI-DAT} 2012, Hsinchu, Taiwan, April 23-25, 2012}, pages = {1--4}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/VLSI-DAT.2012.6212589}, doi = {10.1109/VLSI-DAT.2012.6212589}, timestamp = {Wed, 16 Oct 2019 14:14:54 +0200}, biburl = {https://dblp.org/rec/conf/vlsi-dat/LinTYLWCJHLLS12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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