BibTeX record conf/vlsic/0001CSUM12

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@inproceedings{DBLP:conf/vlsic/0001CSUM12,
  author       = {Yan Zhu and
                  Chi{-}Hang Chan and
                  Sai{-}Weng Sin and
                  Seng{-}Pan U and
                  Rui Paulo Martins},
  title        = {A 34fJ 10b 500 MS/s partial-interleaving pipelined {SAR} {ADC}},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
                  13-15, 2012},
  pages        = {90--91},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/VLSIC.2012.6243804},
  doi          = {10.1109/VLSIC.2012.6243804},
  timestamp    = {Tue, 29 Dec 2020 18:28:28 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsic/0001CSUM12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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