BibTeX record conf/vlsic/Chan0SUM12

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@inproceedings{DBLP:conf/vlsic/Chan0SUM12,
  author       = {Chi{-}Hang Chan and
                  Yan Zhu and
                  Sai{-}Weng Sin and
                  Seng{-}Pan U and
                  Rui Paulo Martins},
  title        = {A 3.8mW 8b 1GS/s 2b/cycle interleaving {SAR} {ADC} with compact {DAC}
                  structure},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
                  13-15, 2012},
  pages        = {86--87},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/VLSIC.2012.6243802},
  doi          = {10.1109/VLSIC.2012.6243802},
  timestamp    = {Tue, 29 Dec 2020 18:28:28 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsic/Chan0SUM12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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