BibTeX record conf/vlsic/KawasumiTHKTNSY12

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@inproceedings{DBLP:conf/vlsic/KawasumiTHKTNSY12,
  author       = {Atsushi Kawasumi and
                  Yasuhisa Takeyama and
                  Osamu Hirabayashi and
                  Keiichi Kushida and
                  Fumihiko Tachibana and
                  Yusuke Niki and
                  Shinichi Sasaki and
                  Tomoaki Yabe},
  title        = {A 47{\%} access time reduction with a worst-case timing-generation
                  scheme utilizing a statistical method for ultra low voltage SRAMs},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
                  13-15, 2012},
  pages        = {100--101},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/VLSIC.2012.6243809},
  doi          = {10.1109/VLSIC.2012.6243809},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/KawasumiTHKTNSY12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}