BibTeX record journals/integration/ZhangS08

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@article{DBLP:journals/integration/ZhangS08,
  author       = {Tianpei Zhang and
                  Sachin S. Sapatnekar},
  title        = {Buffering global interconnects in structured {ASIC} design},
  journal      = {Integr.},
  volume       = {41},
  number       = {2},
  pages        = {171--182},
  year         = {2008},
  url          = {https://doi.org/10.1016/j.vlsi.2007.04.002},
  doi          = {10.1016/J.VLSI.2007.04.002},
  timestamp    = {Thu, 20 Feb 2020 13:22:30 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/ZhangS08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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