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BibTeX record journals/tcad/HameedBH16
@article{DBLP:journals/tcad/HameedBH16, author = {Fazal Hameed and Lars Bauer and J{\"{o}}rg Henkel}, title = {Architecting On-Chip {DRAM} Cache for Simultaneous Miss Rate and Latency Reduction}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {651--664}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488488}, doi = {10.1109/TCAD.2015.2488488}, timestamp = {Mon, 05 Feb 2024 20:23:14 +0100}, biburl = {https://dblp.org/rec/journals/tcad/HameedBH16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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