"An area estimation methodology for FPGA based designs at systemc-level."

Carlo Brandolese, William Fornaciari, Fabio Salice (2004)

> Home

Details and statistics

DOI: 10.1145/996566.996606

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/dac/BrandoleseFS04
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dac/BrandoleseFS04
Carlo Brandolese, William Fornaciari, Fabio Salice:
An area estimation methodology for FPGA based designs at systemc-level. DAC 2004: 129-132

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.