"Streamline verification process with formal property verification to meet ..."

Prosenjit Chatterjee (2005)

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DOI: 10.1145/1065579.1065757

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Prosenjit Chatterjee:
Streamline verification process with formal property verification to meet highly compressed design cycle. DAC 2005: 674-677

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