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"Combine and top down block placement algorithm for hierarchical logic VLSI ..."
Tokinori Kozawa, Chihei Miura, Hidekazu Terai (1984)
- Tokinori Kozawa, Chihei Miura, Hidekazu Terai:

Combine and top down block placement algorithm for hierarchical logic VLSI layout. DAC 1984: 667-669

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